Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
243434 |
1 |
|
T4 |
17 |
|
T7 |
12 |
|
T5 |
1 |
full_word |
530500 |
1 |
|
T4 |
7 |
|
T34 |
80 |
|
T7 |
4 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
773674 |
1 |
|
T4 |
24 |
|
T34 |
80 |
|
T7 |
16 |
auto[TlIntgErrCmd] |
86 |
1 |
|
T60 |
2 |
|
T62 |
5 |
|
T91 |
5 |
auto[TlIntgErrData] |
79 |
1 |
|
T60 |
5 |
|
T62 |
7 |
|
T91 |
3 |
auto[TlIntgErrBoth] |
95 |
1 |
|
T60 |
3 |
|
T62 |
8 |
|
T91 |
2 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
453903 |
1 |
|
T34 |
80 |
|
T7 |
1 |
|
T8 |
6 |
auto[1] |
320031 |
1 |
|
T4 |
24 |
|
T7 |
15 |
|
T5 |
1 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
185404 |
1 |
|
T7 |
1 |
|
T8 |
2 |
|
T30 |
1 |
auto[TlIntgErrNone] |
partial |
auto[1] |
57793 |
1 |
|
T4 |
17 |
|
T7 |
11 |
|
T5 |
1 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
268389 |
1 |
|
T34 |
80 |
|
T8 |
4 |
|
T30 |
1 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
262088 |
1 |
|
T4 |
7 |
|
T7 |
4 |
|
T6 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
29 |
1 |
|
T60 |
2 |
|
T62 |
1 |
|
T91 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
48 |
1 |
|
T62 |
4 |
|
T91 |
3 |
|
T93 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
T91 |
1 |
|
T94 |
1 |
|
T181 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
T94 |
1 |
|
T176 |
1 |
|
T174 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
33 |
1 |
|
T60 |
3 |
|
T62 |
2 |
|
T91 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
43 |
1 |
|
T60 |
2 |
|
T62 |
5 |
|
T91 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
2 |
1 |
|
T179 |
1 |
|
T177 |
1 |
|
- |
- |
auto[TlIntgErrData] |
full_word |
auto[1] |
1 |
1 |
|
T91 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
38 |
1 |
|
T62 |
6 |
|
T93 |
1 |
|
T94 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
46 |
1 |
|
T60 |
2 |
|
T62 |
2 |
|
T91 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
5 |
1 |
|
T60 |
1 |
|
T182 |
1 |
|
T183 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
6 |
1 |
|
T93 |
1 |
|
T94 |
2 |
|
T184 |
2 |