Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8207626 8206338 0 0
selKnown1 61342853 61341565 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8207626 8206338 0 0
T1 27756 27752 0 0
T2 25531 25527 0 0
T3 16852 16848 0 0
T4 61507 61503 0 0
T5 0 42 0 0
T6 0 11 0 0
T7 0 17 0 0
T21 0 26 0 0
T25 29841 29837 0 0
T27 0 8 0 0
T36 267 263 0 0
T43 556 552 0 0
T44 30040 30036 0 0
T45 561 557 0 0
T46 21073 21069 0 0
T56 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 61342853 61341565 0 0
T1 291150 291146 0 0
T2 124493 124489 0 0
T3 297108 297104 0 0
T4 886293 886289 0 0
T5 0 6 0 0
T6 0 8 0 0
T7 0 8 0 0
T21 0 10 0 0
T25 463685 463681 0 0
T27 0 8 0 0
T36 10620 10616 0 0
T43 3667 3663 0 0
T44 153251 153247 0 0
T45 1931 1927 0 0
T46 693383 693379 0 0
T56 0 10 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2206662 2206449 0 0
selKnown1 55342681 55342468 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2206662 2206449 0 0
T1 13875 13874 0 0
T2 12762 12761 0 0
T3 8425 8424 0 0
T4 30737 30736 0 0
T25 14917 14916 0 0
T36 132 131 0 0
T43 277 276 0 0
T44 15019 15018 0 0
T45 279 278 0 0
T46 10535 10534 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55342468 0 0
T1 277269 277268 0 0
T2 111725 111724 0 0
T3 288681 288680 0 0
T4 855542 855541 0 0
T25 448762 448761 0 0
T36 10486 10485 0 0
T43 3388 3387 0 0
T44 138230 138229 0 0
T45 1650 1649 0 0
T46 682846 682845 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 752 539 0 0
selKnown1 572 359 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 752 539 0 0
T1 3 2 0 0
T2 3 2 0 0
T3 1 0 0 0
T4 16 15 0 0
T5 0 21 0 0
T6 0 4 0 0
T7 0 6 0 0
T21 0 9 0 0
T25 3 2 0 0
T27 0 4 0 0
T36 1 0 0 0
T43 1 0 0 0
T44 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T56 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 572 359 0 0
T1 3 2 0 0
T2 3 2 0 0
T3 1 0 0 0
T4 7 6 0 0
T5 0 3 0 0
T6 0 4 0 0
T7 0 4 0 0
T21 0 5 0 0
T25 3 2 0 0
T27 0 4 0 0
T36 1 0 0 0
T43 1 0 0 0
T44 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T56 0 5 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5998223 5997792 0 0
selKnown1 5998014 5997583 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5998223 5997792 0 0
T1 13875 13874 0 0
T2 12763 12762 0 0
T3 8425 8424 0 0
T4 30738 30737 0 0
T25 14918 14917 0 0
T36 133 132 0 0
T43 277 276 0 0
T44 15019 15018 0 0
T45 280 279 0 0
T46 10536 10535 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 5998014 5997583 0 0
T1 13875 13874 0 0
T2 12762 12761 0 0
T3 8425 8424 0 0
T4 30737 30736 0 0
T25 14917 14916 0 0
T36 132 131 0 0
T43 277 276 0 0
T44 15019 15018 0 0
T45 279 278 0 0
T46 10535 10534 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1989 1558 0 0
selKnown1 1586 1155 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1989 1558 0 0
T1 3 2 0 0
T2 3 2 0 0
T3 1 0 0 0
T4 16 15 0 0
T5 0 21 0 0
T6 0 7 0 0
T7 0 11 0 0
T21 0 17 0 0
T25 3 2 0 0
T27 0 4 0 0
T36 1 0 0 0
T43 1 0 0 0
T44 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T56 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1586 1155 0 0
T1 3 2 0 0
T2 3 2 0 0
T3 1 0 0 0
T4 7 6 0 0
T5 0 3 0 0
T6 0 4 0 0
T7 0 4 0 0
T21 0 5 0 0
T25 3 2 0 0
T27 0 4 0 0
T36 1 0 0 0
T43 1 0 0 0
T44 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T56 0 5 0 0

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