Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	194905	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	555758	1		T1	13		T2	1		T4	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	463687	1		T1	12		T5	6		T17	6
values[0x0]	139992	1		T1	13		T2	5		T4	6
values[0x1]	146984	1		T1	7		T2	5		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148512	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	602151	1		T1	15		T2	2		T4	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3999	1		T58	3		T60	128		T56	31
valid_sources[0x01]	3111	1		T17	1		T58	2		T60	384
valid_sources[0x02]	3201	1		T58	3		T60	384		T56	23
valid_sources[0x03]	2512	1		T141	1		T58	2		T60	256
valid_sources[0x04]	2434	1		T189	2		T60	128		T56	23
valid_sources[0x05]	2697	1		T27	1		T58	4		T60	128
valid_sources[0x06]	2710	1		T58	3		T60	128		T56	12
valid_sources[0x07]	2706	1		T4	1		T17	1		T24	1
valid_sources[0x08]	2609	1		T154	1		T58	2		T60	256
valid_sources[0x09]	2497	1		T152	1		T24	1		T58	1
valid_sources[0x0a]	3258	1		T58	3		T60	384		T56	15
valid_sources[0x0b]	3052	1		T18	1		T39	4		T141	2
valid_sources[0x0c]	2672	1		T5	18		T71	2		T190	1
valid_sources[0x0d]	2778	1		T191	2		T58	2		T56	23
valid_sources[0x0e]	3071	1		T43	1		T71	1		T189	1
valid_sources[0x0f]	2718	1		T38	3		T10	1		T192	2
valid_sources[0x10]	3411	1		T24	1		T58	7		T60	256
valid_sources[0x11]	2690	1		T192	2		T58	4		T60	128
valid_sources[0x12]	3104	1		T35	2		T71	1		T10	1
valid_sources[0x13]	2189	1		T152	1		T9	3		T58	2
valid_sources[0x14]	3370	1		T25	5		T58	5		T60	384
valid_sources[0x15]	3003	1		T191	1		T60	512		T56	31
valid_sources[0x16]	3038	1		T142	1		T26	3		T193	1
valid_sources[0x17]	2477	1		T8	1		T142	1		T194	1
valid_sources[0x18]	3535	1		T58	1		T60	128		T56	28
valid_sources[0x19]	2708	1		T152	1		T58	4		T60	384
valid_sources[0x1a]	3249	1		T71	1		T58	1		T60	512
valid_sources[0x1b]	2611	1		T58	2		T56	21		T57	1
valid_sources[0x1c]	2643	1		T44	1		T58	2		T60	384
valid_sources[0x1d]	2971	1		T142	1		T71	1		T58	2
valid_sources[0x1e]	3219	1		T60	128		T56	13		T57	6
valid_sources[0x1f]	2920	1		T140	1		T58	2		T60	256
valid_sources[0x20]	2960	1		T44	2		T140	1		T58	3
valid_sources[0x21]	2820	1		T23	2		T71	1		T20	5
valid_sources[0x22]	3496	1		T141	1		T22	2		T58	4
valid_sources[0x23]	2802	1		T143	1		T142	1		T58	2
valid_sources[0x24]	2940	1		T58	5		T60	384		T56	21
valid_sources[0x25]	2786	1		T90	7		T38	1		T24	1
valid_sources[0x26]	3051	1		T8	3		T21	1		T150	1
valid_sources[0x27]	3038	1		T40	2		T190	4		T192	1
valid_sources[0x28]	2588	1		T38	2		T45	1		T58	2
valid_sources[0x29]	2521	1		T10	1		T58	1		T60	256
valid_sources[0x2a]	3067	1		T10	1		T58	1		T60	384
valid_sources[0x2b]	3297	1		T17	2		T18	1		T10	1
valid_sources[0x2c]	3217	1		T58	3		T60	256		T56	7
valid_sources[0x2d]	2801	1		T140	1		T39	8		T71	2
valid_sources[0x2e]	2929	1		T34	40		T58	3		T60	384
valid_sources[0x2f]	2552	1		T143	1		T140	1		T144	26
valid_sources[0x30]	2629	1		T71	2		T58	8		T60	384
valid_sources[0x31]	2658	1		T8	1		T21	2		T58	4
valid_sources[0x32]	2810	1		T142	1		T192	1		T189	1
valid_sources[0x33]	3503	1		T40	3		T190	1		T192	3
valid_sources[0x34]	3202	1		T24	1		T58	1		T60	128
valid_sources[0x35]	2362	1		T43	4		T58	5		T60	128
valid_sources[0x36]	2976	1		T18	1		T140	1		T58	2
valid_sources[0x37]	2825	1		T38	5		T58	3		T60	640
valid_sources[0x38]	2681	1		T140	1		T71	1		T150	1
valid_sources[0x39]	3414	1		T26	10		T58	1		T60	384
valid_sources[0x3a]	2602	1		T39	1		T71	1		T58	3
valid_sources[0x3b]	2854	1		T71	1		T16	17		T58	5
valid_sources[0x3c]	2884	1		T60	128		T56	39		T57	2
valid_sources[0x3d]	2698	1		T39	1		T58	3		T60	128
valid_sources[0x3e]	2766	1		T71	2		T58	4		T60	256
valid_sources[0x3f]	3058	1		T142	1		T149	7		T58	5
valid_sources[0x40]	2932	1		T91	14		T143	2		T140	3
valid_sources[0x41]	3002	1		T154	1		T189	2		T58	1
valid_sources[0x42]	2752	1		T58	2		T56	11		T57	4
valid_sources[0x43]	2618	1		T134	17		T60	256		T56	14
valid_sources[0x44]	2894	1		T17	1		T58	2		T60	384
valid_sources[0x45]	3019	1		T195	1		T58	2		T60	384
valid_sources[0x46]	2645	1		T8	4		T60	384		T56	21
valid_sources[0x47]	2525	1		T58	3		T56	15		T57	4
valid_sources[0x48]	2628	1		T58	1		T60	256		T56	23
valid_sources[0x49]	2797	1		T71	1		T58	2		T60	255
valid_sources[0x4a]	2354	1		T143	1		T154	2		T58	3
valid_sources[0x4b]	2732	1		T142	1		T10	1		T58	1
valid_sources[0x4c]	2394	1		T18	1		T41	1		T24	2
valid_sources[0x4d]	4865	1		T2	2		T4	1		T196	1
valid_sources[0x4e]	3032	1		T142	1		T71	2		T189	2
valid_sources[0x4f]	2279	1		T58	2		T56	10		T57	1
valid_sources[0x50]	3363	1		T4	2		T71	1		T40	1
valid_sources[0x51]	3536	1		T8	3		T58	2		T60	384
valid_sources[0x52]	2495	1		T193	2		T58	2		T60	128
valid_sources[0x53]	2607	1		T141	1		T58	2		T56	30
valid_sources[0x54]	2948	1		T18	1		T154	1		T60	256
valid_sources[0x55]	3422	1		T58	2		T60	512		T56	12
valid_sources[0x56]	3036	1		T155	11		T71	1		T58	3
valid_sources[0x57]	3614	1		T141	1		T58	6		T60	384
valid_sources[0x58]	3561	1		T39	2		T10	1		T154	1
valid_sources[0x59]	3053	1		T8	4		T145	23		T58	3
valid_sources[0x5a]	2908	1		T58	4		T60	384		T56	15
valid_sources[0x5b]	2841	1		T17	2		T44	1		T71	1
valid_sources[0x5c]	2657	1		T18	1		T39	1		T71	1
valid_sources[0x5d]	3161	1		T14	6		T142	1		T71	2
valid_sources[0x5e]	2829	1		T142	1		T58	3		T60	255
valid_sources[0x5f]	2588	1		T60	256		T56	10		T57	2
valid_sources[0x60]	2976	1		T58	1		T60	383		T56	11
valid_sources[0x61]	2871	1		T71	3		T58	4		T60	256
valid_sources[0x62]	3077	1		T140	1		T71	1		T10	1
valid_sources[0x63]	2912	1		T71	1		T196	1		T150	1
valid_sources[0x64]	3135	1		T58	4		T60	128		T56	13
valid_sources[0x65]	3011	1		T141	3		T58	5		T60	384
valid_sources[0x66]	2835	1		T33	1		T189	1		T193	2
valid_sources[0x67]	3030	1		T196	1		T10	1		T58	4
valid_sources[0x68]	2876	1		T10	1		T58	1		T60	384
valid_sources[0x69]	3259	1		T17	1		T60	895		T56	23
valid_sources[0x6a]	3755	1		T18	1		T58	1		T60	768
valid_sources[0x6b]	2456	1		T140	1		T58	2		T56	20
valid_sources[0x6c]	2916	1		T24	1		T58	4		T60	256
valid_sources[0x6d]	2831	1		T39	2		T58	1		T60	384
valid_sources[0x6e]	2886	1		T140	1		T58	1		T60	128
valid_sources[0x6f]	3141	1		T140	1		T45	1		T52	1
valid_sources[0x70]	2884	1		T58	5		T60	128		T56	25
valid_sources[0x71]	3143	1		T38	3		T142	1		T152	1
valid_sources[0x72]	3463	1		T152	1		T58	2		T60	512
valid_sources[0x73]	3012	1		T39	3		T21	1		T58	1
valid_sources[0x74]	2653	1		T89	2		T40	1		T58	6
valid_sources[0x75]	2775	1		T17	1		T58	3		T60	255
valid_sources[0x76]	3375	1		T58	2		T60	512		T56	13
valid_sources[0x77]	2526	1		T4	1		T33	4		T152	1
valid_sources[0x78]	3147	1		T141	3		T58	2		T60	256
valid_sources[0x79]	3113	1		T197	2		T189	1		T58	3
valid_sources[0x7a]	2757	1		T143	1		T58	5		T56	10
valid_sources[0x7b]	3470	1		T18	1		T10	1		T58	4
valid_sources[0x7c]	2562	1		T38	26		T152	1		T58	1
valid_sources[0x7d]	2385	1		T71	1		T141	1		T58	1
valid_sources[0x7e]	2965	1		T18	1		T149	7		T15	16
valid_sources[0x7f]	2946	1		T18	1		T150	1		T58	2
valid_sources[0x80]	3067	1		T8	2		T150	2		T58	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

279730

1

T1

5

T5

1

T17

4

values[0x0]

all_enables

biggest_size

137992

1

T1

8

T2

1

T4

3

values[0x1]

all_enables

biggest_size

138036

1

T5

1

T17

1

T7

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5045	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	22737	1		T1	7		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10436	1		T58	201		T60	384		T56	34
values[0x0]	8557	1		T1	2		T3	1		T6	1
values[0x1]	8789	1		T1	5		T2	1		T30	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3830	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	23952	1		T1	7		T2	1		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138	1		T198	1		T199	1		T200	1
valid_sources[0x01]	63	1		T58	5		T60	1		T56	1
valid_sources[0x02]	80	1		T58	1		T60	1		T82	12
valid_sources[0x03]	100	1		T201	1		T140	2		T155	2
valid_sources[0x04]	77	1		T202	1		T141	1		T58	3
valid_sources[0x05]	181	1		T203	1		T60	3		T49	84
valid_sources[0x06]	131	1		T204	18		T151	3		T146	1
valid_sources[0x07]	147	1		T205	1		T206	3		T203	1
valid_sources[0x08]	91	1		T3	1		T54	6		T155	1
valid_sources[0x09]	74	1		T18	1		T207	5		T87	3
valid_sources[0x0a]	71	1		T153	5		T208	1		T58	2
valid_sources[0x0b]	74	1		T205	3		T58	3		T60	4
valid_sources[0x0c]	62	1		T51	1		T151	1		T58	1
valid_sources[0x0d]	76	1		T28	1		T58	5		T60	3
valid_sources[0x0e]	68	1		T7	2		T58	6		T60	2
valid_sources[0x0f]	73	1		T200	1		T58	5		T60	7
valid_sources[0x10]	231	1		T146	4		T58	3		T56	1
valid_sources[0x11]	75	1		T209	1		T210	1		T58	5
valid_sources[0x12]	92	1		T211	1		T15	5		T56	1
valid_sources[0x13]	73	1		T58	4		T60	9		T56	1
valid_sources[0x14]	133	1		T212	1		T143	9		T213	1
valid_sources[0x15]	79	1		T214	5		T45	1		T147	1
valid_sources[0x16]	79	1		T215	1		T190	1		T58	4
valid_sources[0x17]	71	1		T53	1		T216	1		T203	1
valid_sources[0x18]	76	1		T53	1		T91	1		T80	1
valid_sources[0x19]	102	1		T59	2		T134	2		T217	1
valid_sources[0x1a]	105	1		T218	1		T216	2		T93	1
valid_sources[0x1b]	258	1		T216	1		T58	4		T60	4
valid_sources[0x1c]	108	1		T11	2		T190	1		T206	1
valid_sources[0x1d]	85	1		T90	4		T8	1		T219	2
valid_sources[0x1e]	106	1		T218	1		T220	1		T58	4
valid_sources[0x1f]	80	1		T221	1		T60	8		T85	5
valid_sources[0x20]	94	1		T133	17		T210	3		T58	5
valid_sources[0x21]	140	1		T212	1		T18	1		T222	1
valid_sources[0x22]	123	1		T9	1		T58	4		T60	1
valid_sources[0x23]	86	1		T165	1		T223	1		T224	1
valid_sources[0x24]	61	1		T32	1		T163	2		T225	3
valid_sources[0x25]	69	1		T6	1		T226	1		T227	7
valid_sources[0x26]	107	1		T228	2		T156	1		T199	1
valid_sources[0x27]	96	1		T46	11		T32	1		T213	1
valid_sources[0x28]	92	1		T229	3		T58	3		T60	2
valid_sources[0x29]	425	1		T145	1		T58	4		T60	2
valid_sources[0x2a]	138	1		T59	2		T230	1		T231	4
valid_sources[0x2b]	244	1		T58	3		T60	3		T49	141
valid_sources[0x2c]	79	1		T58	1		T60	1		T96	3
valid_sources[0x2d]	120	1		T73	4		T224	1		T58	2
valid_sources[0x2e]	78	1		T58	5		T82	16		T85	1
valid_sources[0x2f]	344	1		T227	3		T232	4		T58	3
valid_sources[0x30]	79	1		T231	3		T58	6		T60	6
valid_sources[0x31]	78	1		T53	1		T145	2		T58	4
valid_sources[0x32]	92	1		T59	1		T17	3		T149	2
valid_sources[0x33]	275	1		T42	2		T58	4		T60	10
valid_sources[0x34]	61	1		T160	1		T58	4		T60	4
valid_sources[0x35]	98	1		T161	1		T145	2		T58	4
valid_sources[0x36]	158	1		T214	1		T58	1		T60	2
valid_sources[0x37]	63	1		T18	1		T233	2		T173	1
valid_sources[0x38]	80	1		T11	1		T60	3		T94	2
valid_sources[0x39]	78	1		T170	1		T234	2		T217	1
valid_sources[0x3a]	203	1		T226	1		T235	1		T58	2
valid_sources[0x3b]	86	1		T71	10		T213	1		T203	1
valid_sources[0x3c]	66	1		T58	2		T60	1		T49	1
valid_sources[0x3d]	64	1		T226	1		T230	1		T58	4
valid_sources[0x3e]	70	1		T58	3		T60	3		T56	3
valid_sources[0x3f]	86	1		T212	1		T218	3		T221	2
valid_sources[0x40]	82	1		T25	6		T15	1		T60	3
valid_sources[0x41]	192	1		T18	1		T166	6		T150	7
valid_sources[0x42]	72	1		T208	1		T236	1		T58	4
valid_sources[0x43]	101	1		T90	1		T23	1		T10	1
valid_sources[0x44]	120	1		T237	1		T224	1		T58	3
valid_sources[0x45]	64	1		T238	1		T189	1		T58	4
valid_sources[0x46]	73	1		T239	1		T58	3		T60	1
valid_sources[0x47]	66	1		T61	1		T227	2		T199	1
valid_sources[0x48]	79	1		T28	1		T8	1		T38	1
valid_sources[0x49]	57	1		T58	2		T60	9		T56	2
valid_sources[0x4a]	95	1		T202	1		T58	3		T60	1
valid_sources[0x4b]	109	1		T8	1		T82	40		T50	4
valid_sources[0x4c]	109	1		T141	1		T22	1		T58	2
valid_sources[0x4d]	104	1		T155	1		T240	1		T241	4
valid_sources[0x4e]	497	1		T219	1		T242	1		T243	7
valid_sources[0x4f]	82	1		T209	1		T58	2		T97	1
valid_sources[0x50]	164	1		T244	1		T158	1		T19	1
valid_sources[0x51]	164	1		T220	1		T58	1		T93	1
valid_sources[0x52]	114	1		T245	1		T246	1		T58	5
valid_sources[0x53]	132	1		T218	1		T58	3		T60	1
valid_sources[0x54]	69	1		T247	2		T58	2		T60	4
valid_sources[0x55]	113	1		T141	1		T60	6		T82	31
valid_sources[0x56]	82	1		T201	9		T73	3		T248	1
valid_sources[0x57]	68	1		T224	1		T58	1		T60	4
valid_sources[0x58]	71	1		T29	2		T249	1		T72	1
valid_sources[0x59]	118	1		T152	9		T154	1		T58	3
valid_sources[0x5a]	80	1		T250	1		T148	1		T58	6
valid_sources[0x5b]	127	1		T59	1		T202	1		T159	2
valid_sources[0x5c]	73	1		T58	3		T60	1		T85	1
valid_sources[0x5d]	76	1		T233	1		T251	1		T58	4
valid_sources[0x5e]	83	1		T252	2		T169	2		T58	4
valid_sources[0x5f]	79	1		T253	3		T159	1		T58	1
valid_sources[0x60]	143	1		T5	1		T76	2		T35	1
valid_sources[0x61]	69	1		T10	1		T58	2		T60	1
valid_sources[0x62]	71	1		T58	1		T60	7		T50	3
valid_sources[0x63]	82	1		T195	1		T227	1		T58	4
valid_sources[0x64]	140	1		T58	2		T86	78		T50	2
valid_sources[0x65]	70	1		T68	1		T58	2		T60	1
valid_sources[0x66]	83	1		T219	2		T44	1		T140	5
valid_sources[0x67]	97	1		T254	1		T216	2		T213	1
valid_sources[0x68]	230	1		T244	1		T209	2		T58	2
valid_sources[0x69]	105	1		T58	3		T60	2		T50	2
valid_sources[0x6a]	87	1		T203	1		T58	2		T60	3
valid_sources[0x6b]	141	1		T164	1		T215	1		T40	1
valid_sources[0x6c]	262	1		T13	7		T255	1		T67	14
valid_sources[0x6d]	254	1		T242	2		T149	1		T240	1
valid_sources[0x6e]	71	1		T59	1		T140	1		T66	1
valid_sources[0x6f]	79	1		T206	1		T58	3		T60	1
valid_sources[0x70]	239	1		T251	1		T256	1		T58	5
valid_sources[0x71]	218	1		T7	3		T221	3		T58	1
valid_sources[0x72]	102	1		T212	1		T244	1		T23	1
valid_sources[0x73]	124	1		T218	1		T221	2		T220	1
valid_sources[0x74]	112	1		T59	1		T218	1		T58	4
valid_sources[0x75]	84	1		T10	1		T58	5		T60	7
valid_sources[0x76]	71	1		T214	2		T147	1		T224	1
valid_sources[0x77]	62	1		T203	1		T257	1		T60	2
valid_sources[0x78]	94	1		T37	1		T58	2		T60	1
valid_sources[0x79]	86	1		T234	1		T58	1		T60	1
valid_sources[0x7a]	245	1		T27	1		T258	1		T154	1
valid_sources[0x7b]	66	1		T252	3		T259	1		T227	1
valid_sources[0x7c]	157	1		T42	3		T216	2		T177	1
valid_sources[0x7d]	88	1		T43	9		T176	1		T220	1
valid_sources[0x7e]	97	1		T58	6		T60	2		T93	2
valid_sources[0x7f]	73	1		T224	1		T58	2		T60	1
valid_sources[0x80]	84	1		T221	1		T151	1		T58	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7377

1

T58

196

T60

181

T56

11

values[0x0]

all_enables

biggest_size

7811

1

T1

2

T3

1

T6

1

values[0x1]

all_enables

biggest_size

7549

1

T1

5

T2

1

T30

1