Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	246599	1		T1	19		T2	9		T4	10
full_word	557625	1		T1	13		T2	1		T4	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	803944	1		T1	32		T2	10		T4	13
auto[TlIntgErrCmd]	85	1		T56	2		T85	10		T101	1
auto[TlIntgErrData]	91	1		T56	4		T83	4		T85	4
auto[TlIntgErrBoth]	104	1		T56	4		T83	6		T85	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	465986	1		T1	12		T5	6		T17	6
auto[1]	338238	1		T1	20		T2	10		T4	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	185913	1		T1	7		T5	5		T17	2
auto[TlIntgErrNone]	partial	auto[1]	60429	1		T1	12		T2	9		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	279948	1		T1	5		T5	1		T17	4
auto[TlIntgErrNone]	full_word	auto[1]	277654	1		T1	8		T2	1		T4	3
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T56	1		T85	7		T136	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T56	1		T85	3		T101	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T135	1		T136	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T137	1		T184	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T56	1		T85	2		T101	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T56	2		T83	3		T85	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T56	1		T83	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T181	1		T182	1		T186	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T56	1		T83	3		T85	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T56	3		T83	3		T85	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T85	1		T137	1		T183	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T101	1		T139	1		T183	1