Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	135249434	18518	0	0
late_debug_enable_rd_A	135249434	3394	0	0
late_debug_enable_regwen_rd_A	135249434	3186	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135249434	18518	0	0
T49	549176	2485	0	0
T57	30950	14	0	0
T58	8157	712	0	0
T82	6313	631	0	0
T83	53773	2	0	0
T84	7006	108	0	0
T85	144466	6	0	0
T86	9603	638	0	0
T87	8790	483	0	0
T101	110900	2	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135249434	3394	0	0
T49	549176	376	0	0
T50	209411	374	0	0
T60	732839	415	0	0
T97	11543	8	0	0
T99	19348	41	0	0
T108	23231	6	0	0
T135	49912	47	0	0
T136	56870	35	0	0
T137	92562	28	0	0
T138	13817	68	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135249434	3186	0	0
T49	549176	415	0	0
T50	209411	276	0	0
T60	732839	458	0	0
T97	11543	4	0	0
T108	23231	6	0	0
T135	49912	50	0	0
T136	56870	43	0	0
T137	92562	32	0	0
T138	13817	52	0	0
T139	97352	49	0	0