SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 83.33 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen | 83.33 | 66.67 | 100.00 | ||||
tb.dut.u_reg_regs.u_rsp_intg_gen | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen | 100.00 | 100.00 | 100.00 | ||||
tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
83.33 | 66.67 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
83.33 | 66.67 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.91 | 100.00 | 95.65 | 100.00 | 100.00 | u_reg_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_reg_regs |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_data_intg.u_tlul_data_integ_enc | 100.00 | 100.00 | |||||
gen_rsp_intg.u_rsp_gen | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.33 | 100.00 | 80.00 | 100.00 | u_tlul_err_resp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_data_intg.u_tlul_data_integ_enc | 100.00 | 100.00 | |||||
gen_rsp_intg.u_rsp_gen | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.33 | 100.00 | 80.00 | 100.00 | u_tlul_err_resp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_data_intg.u_tlul_data_integ_enc | 100.00 | 100.00 | |||||
gen_rsp_intg.u_rsp_gen | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.66 | 97.92 | 81.48 | 95.24 | 100.00 | i_tlul_adapter_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_data_intg.u_tlul_data_integ_enc | 100.00 | 100.00 | |||||
gen_rsp_intg.u_rsp_gen | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
SCORE | LINE |
83.33 | 66.67 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 4 | 66.67 | |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 0 | 1 | |
43 | 0 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 1560 | 1560 | 0 | 0 |
PayLoadWidthCheck | 1560 | 1560 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1560 | 1560 | 0 | 0 |
T1 | 5 | 5 | 0 | 0 |
T2 | 5 | 5 | 0 | 0 |
T3 | 5 | 5 | 0 | 0 |
T6 | 5 | 5 | 0 | 0 |
T12 | 5 | 5 | 0 | 0 |
T13 | 5 | 5 | 0 | 0 |
T30 | 5 | 5 | 0 | 0 |
T46 | 5 | 5 | 0 | 0 |
T47 | 5 | 5 | 0 | 0 |
T48 | 5 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1560 | 1560 | 0 | 0 |
T1 | 5 | 5 | 0 | 0 |
T2 | 5 | 5 | 0 | 0 |
T3 | 5 | 5 | 0 | 0 |
T6 | 5 | 5 | 0 | 0 |
T12 | 5 | 5 | 0 | 0 |
T13 | 5 | 5 | 0 | 0 |
T30 | 5 | 5 | 0 | 0 |
T46 | 5 | 5 | 0 | 0 |
T47 | 5 | 5 | 0 | 0 |
T48 | 5 | 5 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 4 | 66.67 | |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 0 | 1 | |
43 | 0 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 441 | 441 | 0 | 0 |
PayLoadWidthCheck | 441 | 441 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 441 | 441 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 441 | 441 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 441 | 441 | 0 | 0 |
PayLoadWidthCheck | 441 | 441 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 441 | 441 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 441 | 441 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 226 | 226 | 0 | 0 |
PayLoadWidthCheck | 226 | 226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 226 | 226 | 0 | 0 |
PayLoadWidthCheck | 226 | 226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
47 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataWidthCheck_A | 226 | 226 | 0 | 0 |
PayLoadWidthCheck | 226 | 226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |