Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54430149 |
5111738 |
0 |
0 |
T1 |
17255 |
6308 |
0 |
0 |
T2 |
61369 |
21040 |
0 |
0 |
T3 |
6119 |
0 |
0 |
0 |
T4 |
0 |
13047 |
0 |
0 |
T5 |
0 |
13480 |
0 |
0 |
T6 |
139361 |
0 |
0 |
0 |
T7 |
0 |
274744 |
0 |
0 |
T12 |
203922 |
0 |
0 |
0 |
T13 |
308675 |
0 |
0 |
0 |
T17 |
0 |
28965 |
0 |
0 |
T30 |
68708 |
0 |
0 |
0 |
T33 |
0 |
97061 |
0 |
0 |
T34 |
0 |
122984 |
0 |
0 |
T42 |
0 |
84304 |
0 |
0 |
T46 |
3152 |
0 |
0 |
0 |
T47 |
9067 |
0 |
0 |
0 |
T48 |
67920 |
0 |
0 |
0 |
T65 |
0 |
5468 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54430149 |
4 |
0 |
0 |
T45 |
21451 |
0 |
0 |
0 |
T51 |
2284 |
2 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T66 |
121959 |
0 |
0 |
0 |
T67 |
1392 |
0 |
0 |
0 |
T68 |
136829 |
0 |
0 |
0 |
T69 |
948564 |
0 |
0 |
0 |
T70 |
594097 |
0 |
0 |
0 |
T71 |
653978 |
0 |
0 |
0 |
T72 |
29516 |
0 |
0 |
0 |
T73 |
1630 |
0 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54430149 |
0 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54430149 |
13551 |
0 |
0 |
T4 |
26857 |
0 |
0 |
0 |
T5 |
63932 |
0 |
0 |
0 |
T6 |
139361 |
121 |
0 |
0 |
T12 |
203922 |
132 |
0 |
0 |
T13 |
308675 |
1260 |
0 |
0 |
T28 |
0 |
17 |
0 |
0 |
T29 |
0 |
55 |
0 |
0 |
T30 |
68708 |
0 |
0 |
0 |
T31 |
0 |
319 |
0 |
0 |
T46 |
3152 |
0 |
0 |
0 |
T47 |
9067 |
0 |
0 |
0 |
T48 |
67920 |
0 |
0 |
0 |
T53 |
5182 |
0 |
0 |
0 |
T61 |
0 |
31 |
0 |
0 |
T74 |
0 |
31 |
0 |
0 |
T75 |
0 |
55 |
0 |
0 |
T76 |
0 |
15 |
0 |
0 |