Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9047754 9046420 0 0
selKnown1 60794250 60792916 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9047754 9046420 0 0
T1 34702 34698 0 0
T2 8173 8169 0 0
T3 1807 1803 0 0
T4 0 8 0 0
T5 0 8 0 0
T6 32482 32478 0 0
T12 33207 33203 0 0
T13 171480 171476 0 0
T17 0 5 0 0
T28 0 8 0 0
T29 0 10 0 0
T30 14526 14522 0 0
T31 0 10 0 0
T46 541 537 0 0
T47 4070 4066 0 0
T48 3000 2996 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 60794250 60792916 0 0
T1 34610 34606 0 0
T2 65456 65452 0 0
T3 7023 7019 0 0
T4 0 8 0 0
T5 0 8 0 0
T6 155603 155599 0 0
T12 220526 220522 0 0
T13 394422 394419 0 0
T17 0 10 0 0
T28 0 8 0 0
T29 0 10 0 0
T30 75967 75963 0 0
T31 0 10 0 0
T46 3423 3419 0 0
T47 11113 11109 0 0
T48 69431 69427 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2682861 2682635 0 0
selKnown1 54430149 54429923 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2682861 2682635 0 0
T1 17347 17346 0 0
T2 4085 4084 0 0
T3 902 901 0 0
T6 16240 16239 0 0
T12 16602 16601 0 0
T13 85733 85732 0 0
T30 7257 7256 0 0
T46 269 268 0 0
T47 2024 2023 0 0
T48 1489 1488 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 54430149 54429923 0 0
T1 17255 17254 0 0
T2 61369 61368 0 0
T3 6119 6118 0 0
T6 139361 139360 0 0
T12 203922 203921 0 0
T13 308675 308675 0 0
T30 68708 68707 0 0
T46 3152 3151 0 0
T47 9067 9066 0 0
T48 67920 67919 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 810 584 0 0
selKnown1 612 386 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 810 584 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 4 0 0
T5 0 4 0 0
T6 1 0 0 0
T12 1 0 0 0
T13 7 6 0 0
T17 0 5 0 0
T28 0 4 0 0
T29 0 5 0 0
T30 1 0 0 0
T31 0 5 0 0
T46 1 0 0 0
T47 11 10 0 0
T48 11 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 612 386 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 4 0 0
T5 0 4 0 0
T6 1 0 0 0
T12 1 0 0 0
T13 7 6 0 0
T17 0 5 0 0
T28 0 4 0 0
T29 0 5 0 0
T30 1 0 0 0
T31 0 5 0 0
T46 1 0 0 0
T47 11 10 0 0
T48 11 10 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6362108 6361667 0 0
selKnown1 6361902 6361461 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6362108 6361667 0 0
T1 17347 17346 0 0
T2 4086 4085 0 0
T3 903 902 0 0
T6 16240 16239 0 0
T12 16603 16602 0 0
T13 85733 85732 0 0
T30 7258 7257 0 0
T46 270 269 0 0
T47 2024 2023 0 0
T48 1489 1488 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6361902 6361461 0 0
T1 17347 17346 0 0
T2 4085 4084 0 0
T3 902 901 0 0
T6 16240 16239 0 0
T12 16602 16601 0 0
T13 85733 85732 0 0
T30 7257 7256 0 0
T46 269 268 0 0
T47 2024 2023 0 0
T48 1489 1488 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1975 1534 0 0
selKnown1 1587 1146 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1975 1534 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 4 0 0
T5 0 4 0 0
T6 1 0 0 0
T12 1 0 0 0
T13 7 6 0 0
T28 0 4 0 0
T29 0 5 0 0
T30 10 9 0 0
T31 0 5 0 0
T46 1 0 0 0
T47 11 10 0 0
T48 11 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1587 1146 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 4 0 0
T5 0 4 0 0
T6 1 0 0 0
T12 1 0 0 0
T13 7 6 0 0
T17 0 5 0 0
T28 0 4 0 0
T29 0 5 0 0
T30 1 0 0 0
T31 0 5 0 0
T46 1 0 0 0
T47 11 10 0 0
T48 11 10 0 0

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