SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 226 | 226 | 0 | 0 |
OutputsKnown_A | 54430149 | 54389347 | 0 | 0 |
gen_no_flops.OutputDelay_A | 54430149 | 54389347 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 54430149 | 54389347 | 0 | 0 |
T1 | 17255 | 16964 | 0 | 0 |
T2 | 61369 | 61288 | 0 | 0 |
T3 | 6119 | 6037 | 0 | 0 |
T6 | 139361 | 139303 | 0 | 0 |
T12 | 203922 | 203863 | 0 | 0 |
T13 | 308675 | 308630 | 0 | 0 |
T30 | 68708 | 68650 | 0 | 0 |
T46 | 3152 | 3095 | 0 | 0 |
T47 | 9067 | 8281 | 0 | 0 |
T48 | 67920 | 67137 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 54430149 | 54389347 | 0 | 0 |
T1 | 17255 | 16964 | 0 | 0 |
T2 | 61369 | 61288 | 0 | 0 |
T3 | 6119 | 6037 | 0 | 0 |
T6 | 139361 | 139303 | 0 | 0 |
T12 | 203922 | 203863 | 0 | 0 |
T13 | 308675 | 308630 | 0 | 0 |
T30 | 68708 | 68650 | 0 | 0 |
T46 | 3152 | 3095 | 0 | 0 |
T47 | 9067 | 8281 | 0 | 0 |
T48 | 67920 | 67137 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |