Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	268253	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	669517	1		T7	7		T4	21		T5	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	599100	1		T7	1		T4	18		T16	6
values[0x0]	165606	1		T7	6		T4	25		T5	3
values[0x1]	173064	1		T7	8		T4	13		T31	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202697	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	735073	1		T7	8		T4	24		T5	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3805	1		T160	2		T74	3		T75	384
valid_sources[0x01]	4045	1		T18	1		T35	1		T17	2
valid_sources[0x02]	3677	1		T23	1		T74	1		T75	640
valid_sources[0x03]	3394	1		T6	4		T17	3		T166	1
valid_sources[0x04]	2975	1		T35	1		T161	1		T162	2
valid_sources[0x05]	3431	1		T7	1		T41	2		T15	1
valid_sources[0x06]	5213	1		T21	1		T156	1		T183	1
valid_sources[0x07]	3032	1		T21	1		T157	3		T74	3
valid_sources[0x08]	3325	1		T14	1		T184	1		T160	1
valid_sources[0x09]	3808	1		T35	2		T15	1		T162	3
valid_sources[0x0a]	3679	1		T14	1		T163	2		T75	128
valid_sources[0x0b]	3149	1		T38	1		T170	2		T74	7
valid_sources[0x0c]	3126	1		T74	12		T75	256		T54	9
valid_sources[0x0d]	2775	1		T17	2		T74	3		T54	6
valid_sources[0x0e]	3761	1		T15	1		T74	2		T75	384
valid_sources[0x0f]	3263	1		T54	12		T72	3		T97	231
valid_sources[0x10]	3147	1		T23	2		T166	1		T163	1
valid_sources[0x11]	3173	1		T14	1		T183	5		T74	2
valid_sources[0x12]	4077	1		T10	1		T185	1		T74	6
valid_sources[0x13]	2934	1		T186	1		T74	3		T75	256
valid_sources[0x14]	3262	1		T169	2		T161	1		T74	3
valid_sources[0x15]	3603	1		T163	1		T74	2		T75	256
valid_sources[0x16]	4066	1		T162	1		T74	3		T75	512
valid_sources[0x17]	3344	1		T10	1		T187	9		T74	1
valid_sources[0x18]	3583	1		T10	1		T14	1		T162	2
valid_sources[0x19]	3583	1		T35	1		T183	8		T188	1
valid_sources[0x1a]	3357	1		T15	4		T74	3		T75	255
valid_sources[0x1b]	3810	1		T163	1		T75	128		T54	6
valid_sources[0x1c]	3583	1		T35	1		T10	1		T163	1
valid_sources[0x1d]	3783	1		T17	1		T10	2		T14	1
valid_sources[0x1e]	2851	1		T155	23		T75	128		T54	6
valid_sources[0x1f]	3266	1		T10	3		T171	1		T74	4
valid_sources[0x20]	4115	1		T10	1		T74	4		T75	255
valid_sources[0x21]	3367	1		T14	1		T15	3		T74	1
valid_sources[0x22]	3248	1		T161	2		T160	4		T74	1
valid_sources[0x23]	3422	1		T156	1		T183	1		T163	1
valid_sources[0x24]	3543	1		T186	1		T74	3		T75	512
valid_sources[0x25]	3124	1		T189	1		T163	2		T74	3
valid_sources[0x26]	3561	1		T161	1		T162	4		T74	2
valid_sources[0x27]	3431	1		T17	1		T23	1		T74	6
valid_sources[0x28]	2948	1		T10	1		T70	1		T54	10
valid_sources[0x29]	3571	1		T190	4		T74	2		T75	256
valid_sources[0x2a]	4156	1		T17	1		T15	1		T166	1
valid_sources[0x2b]	3373	1		T6	2		T38	1		T35	1
valid_sources[0x2c]	3228	1		T7	2		T35	1		T41	10
valid_sources[0x2d]	4101	1		T15	1		T167	18		T74	1
valid_sources[0x2e]	3191	1		T161	1		T74	3		T75	512
valid_sources[0x2f]	3349	1		T184	1		T163	1		T54	6
valid_sources[0x30]	3301	1		T35	1		T23	1		T74	4
valid_sources[0x31]	3950	1		T34	1		T14	1		T74	3
valid_sources[0x32]	2895	1		T35	1		T54	17		T72	3
valid_sources[0x33]	4184	1		T163	2		T75	256		T54	18
valid_sources[0x34]	3787	1		T74	1		T75	128		T54	16
valid_sources[0x35]	3656	1		T7	1		T74	1		T75	256
valid_sources[0x36]	3091	1		T17	1		T189	1		T74	8
valid_sources[0x37]	3232	1		T38	1		T74	3		T75	128
valid_sources[0x38]	3563	1		T10	1		T74	3		T75	384
valid_sources[0x39]	2943	1		T15	1		T75	256		T54	13
valid_sources[0x3a]	3622	1		T21	1		T36	80		T62	1
valid_sources[0x3b]	3178	1		T35	4		T170	2		T160	2
valid_sources[0x3c]	3178	1		T184	2		T74	3		T75	640
valid_sources[0x3d]	2925	1		T16	44		T10	1		T156	2
valid_sources[0x3e]	3331	1		T17	1		T186	1		T160	4
valid_sources[0x3f]	3497	1		T18	1		T35	2		T17	1
valid_sources[0x40]	4039	1		T38	1		T35	1		T23	1
valid_sources[0x41]	3458	1		T17	1		T15	1		T161	1
valid_sources[0x42]	4289	1		T188	1		T166	1		T74	2
valid_sources[0x43]	3878	1		T7	1		T35	1		T74	2
valid_sources[0x44]	3446	1		T21	4		T74	2		T75	128
valid_sources[0x45]	3851	1		T35	4		T163	1		T74	4
valid_sources[0x46]	3475	1		T163	2		T74	6		T75	128
valid_sources[0x47]	3536	1		T15	1		T183	1		T163	1
valid_sources[0x48]	3773	1		T170	3		T74	5		T75	512
valid_sources[0x49]	3790	1		T171	1		T74	4		T75	384
valid_sources[0x4a]	2718	1		T17	1		T162	1		T75	256
valid_sources[0x4b]	3888	1		T10	1		T74	10		T75	128
valid_sources[0x4c]	3956	1		T74	4		T75	640		T54	9
valid_sources[0x4d]	3830	1		T161	2		T75	384		T54	8
valid_sources[0x4e]	2719	1		T163	1		T74	3		T54	6
valid_sources[0x4f]	3502	1		T10	2		T74	3		T75	256
valid_sources[0x50]	3757	1		T161	1		T74	4		T75	256
valid_sources[0x51]	2947	1		T191	1		T74	3		T75	128
valid_sources[0x52]	3517	1		T70	3		T160	1		T74	3
valid_sources[0x53]	4500	1		T7	2		T192	18		T163	1
valid_sources[0x54]	3186	1		T23	1		T74	11		T75	128
valid_sources[0x55]	3462	1		T14	1		T188	1		T74	4
valid_sources[0x56]	2612	1		T193	1		T74	3		T75	128
valid_sources[0x57]	3231	1		T6	1		T194	14		T157	2
valid_sources[0x58]	3290	1		T75	256		T54	6		T72	7
valid_sources[0x59]	4128	1		T186	1		T161	1		T183	1
valid_sources[0x5a]	3033	1		T35	1		T30	16		T74	1
valid_sources[0x5b]	3874	1		T10	1		T161	1		T74	2
valid_sources[0x5c]	3906	1		T35	1		T15	1		T12	1
valid_sources[0x5d]	4119	1		T7	2		T6	1		T163	2
valid_sources[0x5e]	3702	1		T159	47		T74	5		T75	128
valid_sources[0x5f]	3719	1		T74	2		T75	256		T54	7
valid_sources[0x60]	3204	1		T23	2		T190	5		T74	2
valid_sources[0x61]	3639	1		T74	2		T75	512		T54	8
valid_sources[0x62]	3317	1		T15	2		T75	128		T54	17
valid_sources[0x63]	4017	1		T21	1		T195	1		T74	2
valid_sources[0x64]	4163	1		T70	4		T163	1		T74	3
valid_sources[0x65]	3218	1		T10	1		T183	1		T74	12
valid_sources[0x66]	3244	1		T35	1		T17	1		T14	1
valid_sources[0x67]	2967	1		T35	3		T21	2		T14	1
valid_sources[0x68]	3189	1		T160	2		T74	4		T75	512
valid_sources[0x69]	2697	1		T6	2		T35	2		T14	1
valid_sources[0x6a]	3609	1		T188	1		T75	256		T54	5
valid_sources[0x6b]	2942	1		T169	1		T155	7		T74	2
valid_sources[0x6c]	2943	1		T156	1		T162	1		T75	128
valid_sources[0x6d]	3163	1		T35	1		T23	1		T196	2
valid_sources[0x6e]	3916	1		T35	1		T10	1		T74	9
valid_sources[0x6f]	3534	1		T17	1		T42	9		T74	14
valid_sources[0x70]	3218	1		T18	1		T23	1		T163	1
valid_sources[0x71]	3423	1		T5	3		T21	2		T186	1
valid_sources[0x72]	4163	1		T35	2		T15	1		T162	1
valid_sources[0x73]	3729	1		T15	2		T169	1		T171	2
valid_sources[0x74]	3473	1		T193	1		T155	1		T162	2
valid_sources[0x75]	3455	1		T38	2		T35	1		T70	7
valid_sources[0x76]	3273	1		T74	9		T75	128		T54	11
valid_sources[0x77]	3660	1		T35	1		T19	7		T162	1
valid_sources[0x78]	3400	1		T35	1		T17	1		T23	1
valid_sources[0x79]	3530	1		T166	1		T74	6		T75	384
valid_sources[0x7a]	3270	1		T35	1		T23	1		T197	8
valid_sources[0x7b]	3482	1		T160	4		T75	512		T54	6
valid_sources[0x7c]	3226	1		T23	1		T186	1		T189	9
valid_sources[0x7d]	4137	1		T35	1		T163	1		T75	384
valid_sources[0x7e]	3212	1		T17	1		T10	1		T160	2
valid_sources[0x7f]	3204	1		T10	2		T186	1		T163	2
valid_sources[0x80]	3146	1		T163	1		T74	2		T75	128

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

343867

1

T7

1

T4

7

T16

3

values[0x0]

all_enables

biggest_size

163078

1

T7

3

T4

9

T5

1

values[0x1]

all_enables

biggest_size

162572

1

T7

3

T4

5

T31

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6020	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	29202	1		T1	1		T2	1		T13	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12656	1		T74	6		T75	384		T54	453
values[0x0]	11020	1		T1	1		T2	1		T13	1
values[0x1]	11546	1		T24	6		T37	2		T25	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4552	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	30670	1		T1	1		T2	1		T13	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	195	1		T16	1		T198	1		T72	1
valid_sources[0x01]	125	1		T199	1		T40	1		T72	1
valid_sources[0x02]	121	1		T200	2		T201	1		T54	30
valid_sources[0x03]	91	1		T202	1		T203	1		T204	8
valid_sources[0x04]	235	1		T205	1		T192	2		T72	1
valid_sources[0x05]	332	1		T206	8		T185	1		T163	1
valid_sources[0x06]	222	1		T156	1		T54	2		T72	1
valid_sources[0x07]	97	1		T97	5		T87	1		T103	3
valid_sources[0x08]	87	1		T57	7		T202	3		T146	1
valid_sources[0x09]	119	1		T29	1		T207	3		T208	8
valid_sources[0x0a]	89	1		T5	1		T209	2		T210	1
valid_sources[0x0b]	92	1		T211	1		T212	1		T97	6
valid_sources[0x0c]	129	1		T63	6		T189	6		T54	34
valid_sources[0x0d]	887	1		T213	4		T72	1		T97	1
valid_sources[0x0e]	127	1		T54	1		T97	3		T103	1
valid_sources[0x0f]	100	1		T214	1		T97	7		T103	3
valid_sources[0x10]	90	1		T215	1		T11	1		T216	1
valid_sources[0x11]	90	1		T169	1		T217	1		T212	2
valid_sources[0x12]	70	1		T218	1		T219	1		T212	1
valid_sources[0x13]	84	1		T220	1		T72	1		T97	3
valid_sources[0x14]	209	1		T83	1		T209	1		T210	1
valid_sources[0x15]	59	1		T149	1		T97	3		T114	1
valid_sources[0x16]	207	1		T72	1		T97	3		T88	1
valid_sources[0x17]	89	1		T54	3		T97	3		T88	1
valid_sources[0x18]	97	1		T221	1		T197	1		T91	4
valid_sources[0x19]	107	1		T24	1		T222	2		T198	1
valid_sources[0x1a]	85	1		T197	1		T72	1		T97	3
valid_sources[0x1b]	854	1		T29	1		T223	2		T215	2
valid_sources[0x1c]	101	1		T14	1		T169	1		T97	8
valid_sources[0x1d]	91	1		T210	1		T92	1		T96	1
valid_sources[0x1e]	84	1		T17	1		T34	1		T198	1
valid_sources[0x1f]	88	1		T33	1		T201	2		T97	2
valid_sources[0x20]	85	1		T214	1		T224	1		T200	5
valid_sources[0x21]	94	1		T9	1		T225	1		T197	1
valid_sources[0x22]	102	1		T156	1		T226	8		T54	1
valid_sources[0x23]	99	1		T202	3		T160	3		T97	1
valid_sources[0x24]	138	1		T28	1		T227	1		T190	1
valid_sources[0x25]	108	1		T16	3		T206	1		T164	6
valid_sources[0x26]	268	1		T7	1		T166	7		T97	3
valid_sources[0x27]	86	1		T228	1		T229	1		T97	1
valid_sources[0x28]	83	1		T7	1		T230	1		T72	1
valid_sources[0x29]	258	1		T7	1		T54	168		T97	1
valid_sources[0x2a]	76	1		T231	1		T230	1		T97	3
valid_sources[0x2b]	97	1		T220	3		T196	5		T145	4
valid_sources[0x2c]	106	1		T232	9		T61	1		T142	1
valid_sources[0x2d]	119	1		T197	1		T54	1		T97	3
valid_sources[0x2e]	99	1		T199	1		T224	1		T212	1
valid_sources[0x2f]	116	1		T169	2		T170	9		T219	1
valid_sources[0x30]	86	1		T144	5		T165	1		T54	1
valid_sources[0x31]	840	1		T214	1		T210	1		T229	1
valid_sources[0x32]	128	1		T68	1		T70	8		T219	1
valid_sources[0x33]	119	1		T211	1		T97	4		T91	1
valid_sources[0x34]	76	1		T58	1		T223	1		T72	2
valid_sources[0x35]	120	1		T52	1		T220	2		T53	2
valid_sources[0x36]	98	1		T215	1		T233	2		T72	2
valid_sources[0x37]	111	1		T25	1		T234	12		T163	1
valid_sources[0x38]	89	1		T52	1		T151	2		T97	1
valid_sources[0x39]	160	1		T219	1		T54	2		T72	2
valid_sources[0x3a]	92	1		T27	1		T72	1		T97	3
valid_sources[0x3b]	73	1		T229	1		T54	2		T103	2
valid_sources[0x3c]	130	1		T215	1		T156	1		T69	1
valid_sources[0x3d]	203	1		T21	4		T97	1		T107	3
valid_sources[0x3e]	97	1		T52	1		T167	1		T159	1
valid_sources[0x3f]	76	1		T220	1		T72	1		T97	3
valid_sources[0x40]	127	1		T155	6		T188	6		T74	1
valid_sources[0x41]	188	1		T192	1		T74	1		T54	123
valid_sources[0x42]	158	1		T169	1		T97	6		T103	4
valid_sources[0x43]	130	1		T215	1		T54	31		T72	2
valid_sources[0x44]	57	1		T210	1		T72	3		T101	1
valid_sources[0x45]	167	1		T235	1		T198	1		T97	2
valid_sources[0x46]	172	1		T212	1		T72	1		T98	2
valid_sources[0x47]	115	1		T29	2		T228	1		T97	5
valid_sources[0x48]	145	1		T228	3		T236	1		T54	1
valid_sources[0x49]	147	1		T54	2		T72	1		T97	3
valid_sources[0x4a]	76	1		T6	6		T198	1		T72	1
valid_sources[0x4b]	93	1		T237	2		T163	1		T54	1
valid_sources[0x4c]	114	1		T238	1		T192	1		T97	2
valid_sources[0x4d]	122	1		T26	1		T215	1		T239	1
valid_sources[0x4e]	222	1		T19	1		T72	1		T97	2
valid_sources[0x4f]	183	1		T15	1		T97	6		T98	1
valid_sources[0x50]	67	1		T9	2		T237	1		T72	4
valid_sources[0x51]	265	1		T97	4		T88	1		T99	3
valid_sources[0x52]	79	1		T219	1		T72	1		T97	4
valid_sources[0x53]	113	1		T199	1		T167	1		T240	1
valid_sources[0x54]	91	1		T4	5		T241	1		T72	2
valid_sources[0x55]	117	1		T222	2		T167	1		T97	2
valid_sources[0x56]	153	1		T54	1		T97	5		T114	1
valid_sources[0x57]	162	1		T72	1		T97	4		T94	7
valid_sources[0x58]	110	1		T14	1		T219	1		T54	1
valid_sources[0x59]	253	1		T17	1		T192	1		T142	1
valid_sources[0x5a]	313	1		T242	1		T159	3		T54	1
valid_sources[0x5b]	212	1		T26	1		T31	1		T214	1
valid_sources[0x5c]	114	1		T209	1		T223	1		T198	1
valid_sources[0x5d]	289	1		T143	3		T68	1		T167	1
valid_sources[0x5e]	86	1		T72	1		T97	1		T243	2
valid_sources[0x5f]	88	1		T222	1		T74	1		T97	3
valid_sources[0x60]	194	1		T37	1		T59	2		T194	1
valid_sources[0x61]	199	1		T220	2		T54	1		T72	1
valid_sources[0x62]	82	1		T244	1		T196	1		T72	2
valid_sources[0x63]	85	1		T7	1		T28	1		T72	2
valid_sources[0x64]	105	1		T18	1		T29	1		T245	1
valid_sources[0x65]	187	1		T72	2		T97	3		T103	3
valid_sources[0x66]	219	1		T237	1		T246	3		T162	1
valid_sources[0x67]	156	1		T2	1		T25	2		T199	1
valid_sources[0x68]	233	1		T219	1		T141	1		T54	1
valid_sources[0x69]	88	1		T15	1		T97	2		T101	2
valid_sources[0x6a]	97	1		T39	1		T150	6		T72	2
valid_sources[0x6b]	123	1		T228	1		T157	5		T72	1
valid_sources[0x6c]	75	1		T247	1		T165	1		T72	2
valid_sources[0x6d]	225	1		T224	1		T248	1		T197	2
valid_sources[0x6e]	75	1		T240	1		T54	9		T97	1
valid_sources[0x6f]	81	1		T156	1		T162	1		T97	4
valid_sources[0x70]	175	1		T7	1		T249	2		T97	2
valid_sources[0x71]	198	1		T1	1		T169	1		T197	1
valid_sources[0x72]	90	1		T24	1		T219	1		T165	1
valid_sources[0x73]	73	1		T81	1		T14	2		T250	5
valid_sources[0x74]	204	1		T220	2		T147	1		T68	1
valid_sources[0x75]	84	1		T14	1		T54	2		T72	1
valid_sources[0x76]	79	1		T17	1		T251	8		T97	2
valid_sources[0x77]	108	1		T214	1		T201	2		T97	2
valid_sources[0x78]	113	1		T24	1		T52	1		T74	1
valid_sources[0x79]	69	1		T215	1		T97	1		T103	2
valid_sources[0x7a]	81	1		T72	1		T97	4		T88	1
valid_sources[0x7b]	118	1		T97	1		T114	2		T95	1
valid_sources[0x7c]	94	1		T67	16		T252	1		T72	2
valid_sources[0x7d]	75	1		T54	1		T72	2		T97	1
valid_sources[0x7e]	243	1		T42	1		T162	2		T72	1
valid_sources[0x7f]	73	1		T29	1		T253	1		T151	1
valid_sources[0x80]	87	1		T46	1		T202	1		T254	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9127

1

T74

3

T75

198

T54

427

values[0x0]

all_enables

biggest_size

10062

1

T1

1

T2

1

T13

1

values[0x1]

all_enables

biggest_size

10013

1

T24

6

T25

1

T8

1