Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
337014 |
1 |
|
T7 |
8 |
|
T4 |
35 |
|
T5 |
2 |
full_word |
672471 |
1 |
|
T7 |
7 |
|
T4 |
21 |
|
T5 |
1 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
1009185 |
1 |
|
T7 |
15 |
|
T4 |
56 |
|
T5 |
3 |
auto[TlIntgErrCmd] |
101 |
1 |
|
T87 |
4 |
|
T88 |
2 |
|
T107 |
4 |
auto[TlIntgErrData] |
106 |
1 |
|
T87 |
2 |
|
T88 |
11 |
|
T107 |
3 |
auto[TlIntgErrBoth] |
93 |
1 |
|
T87 |
4 |
|
T88 |
7 |
|
T107 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
602699 |
1 |
|
T7 |
1 |
|
T4 |
18 |
|
T16 |
6 |
auto[1] |
406786 |
1 |
|
T7 |
14 |
|
T4 |
38 |
|
T5 |
3 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
1 |
15 |
93.75 |
1 |
Automatically Generated Cross Bins for cr_all
Uncovered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER |
[auto[TlIntgErrCmd]] |
[full_word] |
[auto[0]] |
0 |
1 |
1 |
Covered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
258359 |
1 |
|
T4 |
11 |
|
T16 |
3 |
|
T9 |
1 |
auto[TlIntgErrNone] |
partial |
auto[1] |
78373 |
1 |
|
T7 |
8 |
|
T4 |
24 |
|
T5 |
2 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
344206 |
1 |
|
T7 |
1 |
|
T4 |
7 |
|
T16 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
328247 |
1 |
|
T7 |
6 |
|
T4 |
14 |
|
T5 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
45 |
1 |
|
T87 |
1 |
|
T107 |
2 |
|
T92 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
51 |
1 |
|
T87 |
3 |
|
T88 |
1 |
|
T107 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
5 |
1 |
|
T88 |
1 |
|
T173 |
1 |
|
T174 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
49 |
1 |
|
T88 |
5 |
|
T107 |
3 |
|
T92 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
49 |
1 |
|
T87 |
2 |
|
T88 |
5 |
|
T92 |
5 |
auto[TlIntgErrData] |
full_word |
auto[0] |
5 |
1 |
|
T88 |
1 |
|
T174 |
1 |
|
T136 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
3 |
1 |
|
T92 |
1 |
|
T175 |
1 |
|
T176 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
32 |
1 |
|
T87 |
1 |
|
T88 |
2 |
|
T107 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
56 |
1 |
|
T87 |
3 |
|
T88 |
4 |
|
T107 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
T88 |
1 |
|
T177 |
1 |
|
T178 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
2 |
1 |
|
T136 |
2 |
|
- |
- |
|
- |
- |