Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.87	100.00	59.57	92.28		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	137468135	25264	0	0
late_debug_enable_rd_A	137468135	2772	0	0
late_debug_enable_regwen_rd_A	137468135	2625	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137468135	25264	0	0
T54	128567	2510	0	0
T72	91683	65	0	0
T73	185259	11	0	0
T87	38325	3	0	0
T88	101570	4	0	0
T90	319667	208	0	0
T91	338838	37	0	0
T92	140175	3	0	0
T93	71349	45	0	0
T107	86382	2	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137468135	2772	0	0
T75	499849	254	0	0
T92	140175	71	0	0
T94	17563	142	0	0
T98	21129	1	0	0
T100	23161	9	0	0
T111	8528	10	0	0
T116	26452	12	0	0
T129	38163	56	0	0
T133	192253	45	0	0
T134	25795	2	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137468135	2625	0	0
T75	499849	250	0	0
T92	140175	109	0	0
T94	17563	97	0	0
T98	21129	17	0	0
T100	23161	2	0	0
T116	26452	32	0	0
T129	38163	50	0	0
T133	192253	21	0	0
T135	83543	93	0	0
T136	126279	104	0	0