Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48793519 |
5339099 |
0 |
0 |
T4 |
637681 |
289359 |
0 |
0 |
T5 |
41802 |
28517 |
0 |
0 |
T6 |
447933 |
60822 |
0 |
0 |
T7 |
22351 |
14337 |
0 |
0 |
T9 |
0 |
72995 |
0 |
0 |
T16 |
0 |
81815 |
0 |
0 |
T18 |
0 |
10965 |
0 |
0 |
T26 |
393347 |
0 |
0 |
0 |
T27 |
11307 |
0 |
0 |
0 |
T31 |
2522 |
0 |
0 |
0 |
T38 |
0 |
1161 |
0 |
0 |
T46 |
0 |
180992 |
0 |
0 |
T47 |
123290 |
0 |
0 |
0 |
T48 |
2642 |
0 |
0 |
0 |
T59 |
0 |
153946 |
0 |
0 |
T60 |
6051 |
0 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48793519 |
7 |
0 |
0 |
T32 |
34310 |
0 |
0 |
0 |
T61 |
12763 |
5 |
0 |
0 |
T62 |
0 |
2 |
0 |
0 |
T63 |
173312 |
0 |
0 |
0 |
T64 |
274401 |
0 |
0 |
0 |
T65 |
109090 |
0 |
0 |
0 |
T66 |
262414 |
0 |
0 |
0 |
T67 |
711512 |
0 |
0 |
0 |
T68 |
270384 |
0 |
0 |
0 |
T69 |
81065 |
0 |
0 |
0 |
T70 |
122903 |
0 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48793519 |
0 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48793519 |
10478 |
0 |
0 |
T1 |
254712 |
72 |
0 |
0 |
T2 |
231651 |
26 |
0 |
0 |
T3 |
38067 |
0 |
0 |
0 |
T7 |
22351 |
0 |
0 |
0 |
T8 |
20224 |
0 |
0 |
0 |
T13 |
39035 |
92 |
0 |
0 |
T24 |
145130 |
33 |
0 |
0 |
T25 |
17793 |
5 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T28 |
0 |
252 |
0 |
0 |
T37 |
1528 |
0 |
0 |
0 |
T45 |
2723 |
0 |
0 |
0 |
T47 |
0 |
31 |
0 |
0 |
T57 |
0 |
74 |
0 |
0 |
T58 |
0 |
32 |
0 |
0 |