Line Coverage for Module :
tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
ALWAYS | 95 | 6 | 6 | 100.00 |
ALWAYS | 101 | 8 | 8 | 100.00 |
ALWAYS | 141 | 6 | 6 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
ALWAYS | 218 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
77 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
91 |
1 |
1 |
95 |
2 |
2 |
96 |
2 |
2 |
97 |
2 |
2 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
149 |
1 |
1 |
150 |
1 |
1 |
154 |
1 |
1 |
204 |
1 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
223 |
1 |
1 |
Line Coverage for Module :
tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 48 | 47 | 97.92 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
ALWAYS | 95 | 6 | 6 | 100.00 |
ALWAYS | 101 | 8 | 8 | 100.00 |
ALWAYS | 116 | 11 | 11 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
ALWAYS | 186 | 4 | 3 | 75.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
ALWAYS | 218 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
77 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
91 |
1 |
1 |
95 |
2 |
2 |
96 |
2 |
2 |
97 |
2 |
2 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
154 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
0 |
1 |
|
|
|
MISSING_ELSE |
192 |
1 |
1 |
204 |
1 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
223 |
1 |
1 |
Cond Coverage for Module :
tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 46 | 44 | 95.65 |
Logical | 46 | 44 | 95.65 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 77
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T2,T13 |
LINE 78
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T13,T37 |
1 | 1 | Covered | T1,T2,T13 |
LINE 80
EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
--1-- ----------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T74,T75,T54 |
1 | 1 | Covered | T1,T2,T13 |
LINE 80
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T45,T7 |
0 | 1 | Covered | T1,T24,T37 |
1 | 0 | Covered | T1,T2,T13 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T24,T37 |
LINE 81
EXPRESSION (a_ack & (tl_i.a_opcode == Get))
--1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T45,T7 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T74,T75,T54 |
LINE 81
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T45,T7 |
LINE 83
EXPRESSION (wr_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T54,T72,T73 |
1 | 1 | Covered | T1,T2,T13 |
LINE 84
EXPRESSION (rd_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T54,T72,T73 |
1 | 1 | Covered | T74,T75,T54 |
LINE 109
EXPRESSION (rd_req ? AccessAckData : AccessAck)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T74,T75,T54 |
LINE 145
EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T74,T75,T54 |
1 | Covered | T1,T2,T13 |
LINE 145
SUB-EXPRESSION (error_i || err_internal || wr_req)
---1--- ------2----- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T74,T75,T54 |
0 | 0 | 1 | Covered | T1,T2,T13 |
0 | 1 | 0 | Covered | T54,T72,T73 |
1 | 0 | 0 | Covered | T54,T87,T88 |
LINE 146
EXPRESSION (error_i || err_internal)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T13 |
0 | 1 | Covered | T54,T72,T73 |
1 | 0 | Covered | T54,T72,T87 |
LINE 154
SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
LINE 154
SUB-EXPRESSION (tl_i.a_valid & busy_i)
------1----- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Unreachable | |
LINE 208
EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
-------1------ ---------2-------- ---3-- -----4----- -----5----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T13 |
0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Covered | T1,T45,T7 |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Covered | T54,T72,T87 |
Cond Coverage for Module :
tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 54 | 44 | 81.48 |
Logical | 54 | 44 | 81.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 77
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Covered | T7,T4,T5 |
LINE 78
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T31,T16,T9 |
1 | 1 | Covered | T7,T4,T5 |
LINE 80
EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
--1-- ----------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T4,T16 |
1 | 1 | Covered | T7,T4,T5 |
LINE 80
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T24,T25,T7 |
0 | 1 | Covered | T3,T13,T25 |
1 | 0 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T13,T25 |
LINE 81
EXPRESSION (a_ack & (tl_i.a_opcode == Get))
--1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T24,T25,T7 |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Covered | T7,T4,T16 |
LINE 81
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T24,T25,T7 |
LINE 83
EXPRESSION (wr_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T4,T5 |
LINE 84
EXPRESSION (rd_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T4,T16 |
LINE 109
EXPRESSION (rd_req ? AccessAckData : AccessAck)
---1--
-1- | Status | Tests |
0 | Covered | T7,T4,T5 |
1 | Covered | T7,T4,T16 |
LINE 134
EXPRESSION ((error_i || error_q || gen_access_latency1.wr_req_q) ? '1 : (gen_access_latency1.rd_req_q ? rdata_i : rdata_q))
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T4,T5 |
LINE 134
SUB-EXPRESSION (error_i || error_q || gen_access_latency1.wr_req_q)
---1--- ---2--- --------------3-------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T7,T4,T5 |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Not Covered | |
LINE 134
SUB-EXPRESSION (gen_access_latency1.rd_req_q ? rdata_i : rdata_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T4,T16 |
LINE 137
EXPRESSION ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q) ? (error_q || error_i) : error_q)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T4,T5 |
LINE 137
SUB-EXPRESSION (gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)
--------------1------------- --------------2-------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T4,T5 |
1 | 0 | Covered | T7,T4,T16 |
LINE 137
SUB-EXPRESSION (error_q || error_i)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T4,T5 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 154
SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T4,T5 |
LINE 154
SUB-EXPRESSION (tl_i.a_valid & busy_i)
------1----- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Unreachable | |
LINE 208
EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
-------1------ ---------2-------- ---3-- -----4----- -----5----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T7,T4,T5 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Covered | T3,T13,T24 |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Not Covered | |
Branch Coverage for Module :
tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=4,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
IF |
95 |
4 |
4 |
100.00 |
IF |
101 |
4 |
4 |
100.00 |
IF |
218 |
2 |
2 |
100.00 |
IF |
141 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
-2-: 96 if (a_ack)
-3-: 97 if (d_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_ni))
-2-: 105 if (a_ack)
-3-: 109 (rd_req) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T74,T75,T54 |
0 |
1 |
0 |
Covered |
T1,T2,T13 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 218 if (wr_req)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T13 |
0 |
Covered |
T1,T2,T13 |
LineNo. Expression
-1-: 141 if ((!rst_ni))
-2-: 144 if (a_ack)
-3-: 145 (((error_i || err_internal) || wr_req)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T1,T2,T13 |
0 |
1 |
0 |
Covered |
T74,T75,T54 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
134 |
3 |
3 |
100.00 |
TERNARY |
137 |
2 |
2 |
100.00 |
IF |
95 |
4 |
4 |
100.00 |
IF |
101 |
4 |
4 |
100.00 |
IF |
218 |
2 |
2 |
100.00 |
IF |
116 |
3 |
3 |
100.00 |
IF |
186 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 134 (((error_i || error_q) || gen_access_latency1.wr_req_q)) ?
-2-: 134 (gen_access_latency1.rd_req_q) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T7,T4,T5 |
0 |
1 |
Covered |
T7,T4,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 137 ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 if ((!rst_ni))
-2-: 96 if (a_ack)
-3-: 97 if (d_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T7,T4,T5 |
0 |
0 |
1 |
Covered |
T7,T4,T5 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_ni))
-2-: 105 if (a_ack)
-3-: 109 (rd_req) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T7,T4,T16 |
0 |
1 |
0 |
Covered |
T7,T4,T5 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 218 if (wr_req)
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 116 if ((!rst_ni))
-2-: 125 if (a_ack)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T7,T4,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 if ((!rst_ni))
-2-: 188 if (intg_error)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_reg
Assertion Details
AllowedLatency_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
677 |
677 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T13 |
2 |
2 |
0 |
0 |
T24 |
2 |
2 |
0 |
0 |
T25 |
2 |
2 |
0 |
0 |
T37 |
2 |
2 |
0 |
0 |
T45 |
2 |
2 |
0 |
0 |
MatchedWidthAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
677 |
677 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T13 |
2 |
2 |
0 |
0 |
T24 |
2 |
2 |
0 |
0 |
T25 |
2 |
2 |
0 |
0 |
T37 |
2 |
2 |
0 |
0 |
T45 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_tlul_adapter_reg
| Line No. | Total | Covered | Percent |
TOTAL | | 48 | 47 | 97.92 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
ALWAYS | 95 | 6 | 6 | 100.00 |
ALWAYS | 101 | 8 | 8 | 100.00 |
ALWAYS | 116 | 11 | 11 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
ALWAYS | 186 | 4 | 3 | 75.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
ALWAYS | 218 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
77 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
91 |
1 |
1 |
95 |
2 |
2 |
96 |
2 |
2 |
97 |
2 |
2 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
134 |
1 |
1 |
137 |
1 |
1 |
154 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
0 |
1 |
|
|
|
MISSING_ELSE |
192 |
1 |
1 |
204 |
1 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
223 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_tlul_adapter_reg
| Total | Covered | Percent |
Conditions | 54 | 44 | 81.48 |
Logical | 54 | 44 | 81.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 77
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Covered | T7,T4,T5 |
LINE 78
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T31,T16,T9 |
1 | 1 | Covered | T7,T4,T5 |
LINE 80
EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
--1-- ----------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T4,T16 |
1 | 1 | Covered | T7,T4,T5 |
LINE 80
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T24,T25,T7 |
0 | 1 | Covered | T3,T13,T25 |
1 | 0 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T13,T25 |
LINE 81
EXPRESSION (a_ack & (tl_i.a_opcode == Get))
--1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T24,T25,T7 |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Covered | T7,T4,T16 |
LINE 81
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T24,T25,T7 |
LINE 83
EXPRESSION (wr_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T4,T5 |
LINE 84
EXPRESSION (rd_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T4,T16 |
LINE 109
EXPRESSION (rd_req ? AccessAckData : AccessAck)
---1--
-1- | Status | Tests |
0 | Covered | T7,T4,T5 |
1 | Covered | T7,T4,T16 |
LINE 134
EXPRESSION ((error_i || error_q || gen_access_latency1.wr_req_q) ? '1 : (gen_access_latency1.rd_req_q ? rdata_i : rdata_q))
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T4,T5 |
LINE 134
SUB-EXPRESSION (error_i || error_q || gen_access_latency1.wr_req_q)
---1--- ---2--- --------------3-------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T7,T4,T5 |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Not Covered | |
LINE 134
SUB-EXPRESSION (gen_access_latency1.rd_req_q ? rdata_i : rdata_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T4,T16 |
LINE 137
EXPRESSION ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q) ? (error_q || error_i) : error_q)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T4,T5 |
LINE 137
SUB-EXPRESSION (gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)
--------------1------------- --------------2-------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T4,T5 |
1 | 0 | Covered | T7,T4,T16 |
LINE 137
SUB-EXPRESSION (error_q || error_i)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T4,T5 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 154
SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T4,T5 |
LINE 154
SUB-EXPRESSION (tl_i.a_valid & busy_i)
------1----- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Unreachable | |
LINE 208
EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
-------1------ ---------2-------- ---3-- -----4----- -----5----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T7,T4,T5 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Covered | T3,T13,T24 |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.i_tlul_adapter_reg
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
134 |
3 |
3 |
100.00 |
TERNARY |
137 |
2 |
2 |
100.00 |
IF |
95 |
4 |
4 |
100.00 |
IF |
101 |
4 |
4 |
100.00 |
IF |
218 |
2 |
2 |
100.00 |
IF |
116 |
3 |
3 |
100.00 |
IF |
186 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 134 (((error_i || error_q) || gen_access_latency1.wr_req_q)) ?
-2-: 134 (gen_access_latency1.rd_req_q) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T7,T4,T5 |
0 |
1 |
Covered |
T7,T4,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 137 ((gen_access_latency1.rd_req_q || gen_access_latency1.wr_req_q)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 if ((!rst_ni))
-2-: 96 if (a_ack)
-3-: 97 if (d_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T7,T4,T5 |
0 |
0 |
1 |
Covered |
T7,T4,T5 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_ni))
-2-: 105 if (a_ack)
-3-: 109 (rd_req) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T7,T4,T16 |
0 |
1 |
0 |
Covered |
T7,T4,T5 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 218 if (wr_req)
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 116 if ((!rst_ni))
-2-: 125 if (a_ack)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T7,T4,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 if ((!rst_ni))
-2-: 188 if (intg_error)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i_tlul_adapter_reg
Assertion Details
AllowedLatency_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
229 |
229 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T37 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
MatchedWidthAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
229 |
229 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T37 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
ALWAYS | 95 | 6 | 6 | 100.00 |
ALWAYS | 101 | 8 | 8 | 100.00 |
ALWAYS | 141 | 6 | 6 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
ALWAYS | 218 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
77 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
91 |
1 |
1 |
95 |
2 |
2 |
96 |
2 |
2 |
97 |
2 |
2 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
149 |
1 |
1 |
150 |
1 |
1 |
154 |
1 |
1 |
204 |
1 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
223 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
| Total | Covered | Percent |
Conditions | 46 | 44 | 95.65 |
Logical | 46 | 44 | 95.65 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 77
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T2,T13 |
LINE 78
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T13,T37 |
1 | 1 | Covered | T1,T2,T13 |
LINE 80
EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
--1-- ----------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T74,T75,T54 |
1 | 1 | Covered | T1,T2,T13 |
LINE 80
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T45,T7 |
0 | 1 | Covered | T1,T24,T37 |
1 | 0 | Covered | T1,T2,T13 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T24,T37 |
LINE 81
EXPRESSION (a_ack & (tl_i.a_opcode == Get))
--1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T45,T7 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T74,T75,T54 |
LINE 81
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T45,T7 |
LINE 83
EXPRESSION (wr_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T54,T72,T73 |
1 | 1 | Covered | T1,T2,T13 |
LINE 84
EXPRESSION (rd_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T54,T72,T73 |
1 | 1 | Covered | T74,T75,T54 |
LINE 109
EXPRESSION (rd_req ? AccessAckData : AccessAck)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T74,T75,T54 |
LINE 145
EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T74,T75,T54 |
1 | Covered | T1,T2,T13 |
LINE 145
SUB-EXPRESSION (error_i || err_internal || wr_req)
---1--- ------2----- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T74,T75,T54 |
0 | 0 | 1 | Covered | T1,T2,T13 |
0 | 1 | 0 | Covered | T54,T72,T73 |
1 | 0 | 0 | Covered | T54,T87,T88 |
LINE 146
EXPRESSION (error_i || err_internal)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T13 |
0 | 1 | Covered | T54,T72,T73 |
1 | 0 | Covered | T54,T72,T87 |
LINE 154
SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
LINE 154
SUB-EXPRESSION (tl_i.a_valid & busy_i)
------1----- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Unreachable | |
LINE 208
EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
-------1------ ---------2-------- ---3-- -----4----- -----5----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T13 |
0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Covered | T1,T45,T7 |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Covered | T54,T72,T87 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
IF |
95 |
4 |
4 |
100.00 |
IF |
101 |
4 |
4 |
100.00 |
IF |
218 |
2 |
2 |
100.00 |
IF |
141 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
-2-: 96 if (a_ack)
-3-: 97 if (d_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_ni))
-2-: 105 if (a_ack)
-3-: 109 (rd_req) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T74,T75,T54 |
0 |
1 |
0 |
Covered |
T1,T2,T13 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 218 if (wr_req)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T13 |
0 |
Covered |
T1,T2,T13 |
LineNo. Expression
-1-: 141 if ((!rst_ni))
-2-: 144 if (a_ack)
-3-: 145 (((error_i || err_internal) || wr_req)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T1,T2,T13 |
0 |
1 |
0 |
Covered |
T74,T75,T54 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
Assertion Details
AllowedLatency_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
448 |
448 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T37 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
MatchedWidthAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
448 |
448 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T37 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |