Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9209191 |
9207837 |
0 |
0 |
selKnown1 |
55443646 |
55442292 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9209191 |
9207837 |
0 |
0 |
T1 |
19003 |
19001 |
0 |
0 |
T2 |
27602 |
27600 |
0 |
0 |
T3 |
5113 |
5111 |
0 |
0 |
T4 |
8 |
6 |
0 |
0 |
T5 |
2 |
0 |
0 |
0 |
T6 |
0 |
10 |
0 |
0 |
T7 |
21181 |
21177 |
0 |
0 |
T8 |
1018 |
1014 |
0 |
0 |
T13 |
19756 |
19754 |
0 |
0 |
T16 |
0 |
10 |
0 |
0 |
T24 |
31899 |
31895 |
0 |
0 |
T25 |
12899 |
12895 |
0 |
0 |
T26 |
10 |
8 |
0 |
0 |
T27 |
2 |
0 |
0 |
0 |
T37 |
1121 |
1117 |
0 |
0 |
T45 |
442 |
438 |
0 |
0 |
T47 |
0 |
8 |
0 |
0 |
T57 |
0 |
12 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55443646 |
55442292 |
0 |
0 |
T1 |
264213 |
264211 |
0 |
0 |
T2 |
245452 |
245450 |
0 |
0 |
T3 |
40623 |
40621 |
0 |
0 |
T4 |
6 |
4 |
0 |
0 |
T5 |
2 |
0 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
32942 |
32938 |
0 |
0 |
T8 |
20734 |
20730 |
0 |
0 |
T13 |
48913 |
48911 |
0 |
0 |
T16 |
0 |
10 |
0 |
0 |
T24 |
161087 |
161083 |
0 |
0 |
T25 |
24245 |
24241 |
0 |
0 |
T26 |
10 |
8 |
0 |
0 |
T27 |
2 |
0 |
0 |
0 |
T37 |
2089 |
2085 |
0 |
0 |
T45 |
2945 |
2941 |
0 |
0 |
T47 |
0 |
8 |
0 |
0 |
T57 |
0 |
12 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2558585 |
2558356 |
0 |
0 |
selKnown1 |
48793519 |
48793290 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2558585 |
2558356 |
0 |
0 |
T1 |
9501 |
9500 |
0 |
0 |
T2 |
13801 |
13800 |
0 |
0 |
T3 |
2556 |
2555 |
0 |
0 |
T7 |
10587 |
10586 |
0 |
0 |
T8 |
508 |
507 |
0 |
0 |
T13 |
9878 |
9877 |
0 |
0 |
T24 |
15941 |
15940 |
0 |
0 |
T25 |
6446 |
6445 |
0 |
0 |
T37 |
559 |
558 |
0 |
0 |
T45 |
220 |
219 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48793519 |
48793290 |
0 |
0 |
T1 |
254712 |
254711 |
0 |
0 |
T2 |
231651 |
231650 |
0 |
0 |
T3 |
38067 |
38066 |
0 |
0 |
T7 |
22351 |
22350 |
0 |
0 |
T8 |
20224 |
20223 |
0 |
0 |
T13 |
39035 |
39034 |
0 |
0 |
T24 |
145130 |
145129 |
0 |
0 |
T25 |
17793 |
17792 |
0 |
0 |
T37 |
1528 |
1527 |
0 |
0 |
T45 |
2723 |
2722 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
659 |
430 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T7 |
3 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T24 |
8 |
7 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
5 |
4 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T57 |
0 |
6 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
626 |
397 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T24 |
8 |
7 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
5 |
4 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T57 |
0 |
6 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6647919 |
6647471 |
0 |
0 |
selKnown1 |
6647719 |
6647271 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6647919 |
6647471 |
0 |
0 |
T1 |
9502 |
9501 |
0 |
0 |
T2 |
13801 |
13800 |
0 |
0 |
T3 |
2557 |
2556 |
0 |
0 |
T7 |
10588 |
10587 |
0 |
0 |
T8 |
508 |
507 |
0 |
0 |
T13 |
9878 |
9877 |
0 |
0 |
T24 |
15942 |
15941 |
0 |
0 |
T25 |
6447 |
6446 |
0 |
0 |
T37 |
560 |
559 |
0 |
0 |
T45 |
220 |
219 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6647719 |
6647271 |
0 |
0 |
T1 |
9501 |
9500 |
0 |
0 |
T2 |
13801 |
13800 |
0 |
0 |
T3 |
2556 |
2555 |
0 |
0 |
T7 |
10587 |
10586 |
0 |
0 |
T8 |
508 |
507 |
0 |
0 |
T13 |
9878 |
9877 |
0 |
0 |
T24 |
15941 |
15940 |
0 |
0 |
T25 |
6446 |
6445 |
0 |
0 |
T37 |
559 |
558 |
0 |
0 |
T45 |
220 |
219 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2028 |
1580 |
0 |
0 |
selKnown1 |
1782 |
1334 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2028 |
1580 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
8 |
0 |
0 |
T7 |
3 |
2 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T24 |
8 |
7 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
5 |
4 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T57 |
0 |
6 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1782 |
1334 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T24 |
8 |
7 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
5 |
4 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T57 |
0 |
6 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |