SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1374 | 1374 | 0 | 0 |
OutputsKnown_A | 292761114 | 292510008 | 0 | 0 |
gen_flops.OutputDelay_A | 146380557 | 146249370 | 0 | 2061 |
gen_no_flops.OutputDelay_A | 146380557 | 146255004 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1374 | 1374 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T25 | 6 | 6 | 0 | 0 |
T37 | 6 | 6 | 0 | 0 |
T45 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 292761114 | 292510008 | 0 | 0 |
T1 | 1528272 | 1527894 | 0 | 0 |
T2 | 1389906 | 1389534 | 0 | 0 |
T3 | 228402 | 228066 | 0 | 0 |
T7 | 134106 | 133452 | 0 | 0 |
T8 | 121344 | 121008 | 0 | 0 |
T13 | 234210 | 233892 | 0 | 0 |
T24 | 870780 | 867282 | 0 | 0 |
T25 | 106758 | 105630 | 0 | 0 |
T37 | 9168 | 8754 | 0 | 0 |
T45 | 16338 | 16020 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 146380557 | 146249370 | 0 | 2061 |
T1 | 764136 | 763938 | 0 | 9 |
T2 | 694953 | 694758 | 0 | 9 |
T3 | 114201 | 114024 | 0 | 9 |
T7 | 67053 | 66708 | 0 | 9 |
T8 | 60672 | 60495 | 0 | 9 |
T13 | 117105 | 116937 | 0 | 9 |
T24 | 435390 | 433569 | 0 | 9 |
T25 | 53379 | 52788 | 0 | 9 |
T37 | 4584 | 4368 | 0 | 9 |
T45 | 8169 | 8001 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 146380557 | 146255004 | 0 | 0 |
T1 | 764136 | 763947 | 0 | 0 |
T2 | 694953 | 694767 | 0 | 0 |
T3 | 114201 | 114033 | 0 | 0 |
T7 | 67053 | 66726 | 0 | 0 |
T8 | 60672 | 60504 | 0 | 0 |
T13 | 117105 | 116946 | 0 | 0 |
T24 | 435390 | 433641 | 0 | 0 |
T25 | 53379 | 52815 | 0 | 0 |
T37 | 4584 | 4377 | 0 | 0 |
T45 | 8169 | 8010 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 229 | 229 | 0 | 0 |
OutputsKnown_A | 48793519 | 48751668 | 0 | 0 |
gen_flops.OutputDelay_A | 48793519 | 48749790 | 0 | 687 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 229 | 229 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48749790 | 0 | 687 |
T1 | 254712 | 254646 | 0 | 3 |
T2 | 231651 | 231586 | 0 | 3 |
T3 | 38067 | 38008 | 0 | 3 |
T7 | 22351 | 22236 | 0 | 3 |
T8 | 20224 | 20165 | 0 | 3 |
T13 | 39035 | 38979 | 0 | 3 |
T24 | 145130 | 144523 | 0 | 3 |
T25 | 17793 | 17596 | 0 | 3 |
T37 | 1528 | 1456 | 0 | 3 |
T45 | 2723 | 2667 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 229 | 229 | 0 | 0 |
OutputsKnown_A | 48793519 | 48751668 | 0 | 0 |
gen_flops.OutputDelay_A | 48793519 | 48749790 | 0 | 687 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 229 | 229 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48749790 | 0 | 687 |
T1 | 254712 | 254646 | 0 | 3 |
T2 | 231651 | 231586 | 0 | 3 |
T3 | 38067 | 38008 | 0 | 3 |
T7 | 22351 | 22236 | 0 | 3 |
T8 | 20224 | 20165 | 0 | 3 |
T13 | 39035 | 38979 | 0 | 3 |
T24 | 145130 | 144523 | 0 | 3 |
T25 | 17793 | 17596 | 0 | 3 |
T37 | 1528 | 1456 | 0 | 3 |
T45 | 2723 | 2667 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 229 | 229 | 0 | 0 |
OutputsKnown_A | 48793519 | 48751668 | 0 | 0 |
gen_no_flops.OutputDelay_A | 48793519 | 48751668 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 229 | 229 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 229 | 229 | 0 | 0 |
OutputsKnown_A | 48793519 | 48751668 | 0 | 0 |
gen_flops.OutputDelay_A | 48793519 | 48749790 | 0 | 687 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 229 | 229 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48749790 | 0 | 687 |
T1 | 254712 | 254646 | 0 | 3 |
T2 | 231651 | 231586 | 0 | 3 |
T3 | 38067 | 38008 | 0 | 3 |
T7 | 22351 | 22236 | 0 | 3 |
T8 | 20224 | 20165 | 0 | 3 |
T13 | 39035 | 38979 | 0 | 3 |
T24 | 145130 | 144523 | 0 | 3 |
T25 | 17793 | 17596 | 0 | 3 |
T37 | 1528 | 1456 | 0 | 3 |
T45 | 2723 | 2667 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 229 | 229 | 0 | 0 |
OutputsKnown_A | 48793519 | 48751668 | 0 | 0 |
gen_no_flops.OutputDelay_A | 48793519 | 48751668 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 229 | 229 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 229 | 229 | 0 | 0 |
OutputsKnown_A | 48793519 | 48751668 | 0 | 0 |
gen_no_flops.OutputDelay_A | 48793519 | 48751668 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 229 | 229 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48793519 | 48751668 | 0 | 0 |
T1 | 254712 | 254649 | 0 | 0 |
T2 | 231651 | 231589 | 0 | 0 |
T3 | 38067 | 38011 | 0 | 0 |
T7 | 22351 | 22242 | 0 | 0 |
T8 | 20224 | 20168 | 0 | 0 |
T13 | 39035 | 38982 | 0 | 0 |
T24 | 145130 | 144547 | 0 | 0 |
T25 | 17793 | 17605 | 0 | 0 |
T37 | 1528 | 1459 | 0 | 0 |
T45 | 2723 | 2670 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |