Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 217580 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 562642 1 T4 2 T7 3 T5 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 504423 1 T4 6 T7 8 T6 1
values[0x0] 135192 1 T4 7 T5 8 T6 11
values[0x1] 140607 1 T4 1 T7 1 T5 10



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 164193 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 616029 1 T4 5 T7 5 T5 6



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2951 1 T189 1 T32 1 T67 2
valid_sources[0x01] 2963 1 T13 1 T190 1 T153 1
valid_sources[0x02] 2758 1 T5 1 T25 1 T36 1
valid_sources[0x03] 2770 1 T34 1 T32 1 T64 3
valid_sources[0x04] 3000 1 T127 1 T13 1 T135 2
valid_sources[0x05] 3060 1 T127 2 T16 1 T191 1
valid_sources[0x06] 2878 1 T25 1 T192 1 T64 10
valid_sources[0x07] 2925 1 T127 3 T64 3 T68 6
valid_sources[0x08] 3185 1 T193 1 T33 3 T67 1
valid_sources[0x09] 2766 1 T19 1 T11 1 T189 1
valid_sources[0x0a] 2852 1 T5 1 T29 1 T11 1
valid_sources[0x0b] 2811 1 T160 1 T167 1 T67 10
valid_sources[0x0c] 2593 1 T11 1 T191 1 T64 6
valid_sources[0x0d] 3206 1 T10 1 T190 1 T20 2
valid_sources[0x0e] 3041 1 T12 1 T193 1 T189 1
valid_sources[0x0f] 3087 1 T21 1 T33 1 T64 7
valid_sources[0x10] 3255 1 T157 1 T64 21 T84 5
valid_sources[0x11] 3046 1 T12 1 T191 1 T67 1
valid_sources[0x12] 3082 1 T150 1 T32 1 T67 4
valid_sources[0x13] 3224 1 T29 1 T33 3 T67 3
valid_sources[0x14] 3149 1 T25 1 T36 3 T13 1
valid_sources[0x15] 2871 1 T67 1 T64 8 T68 2
valid_sources[0x16] 3077 1 T189 1 T67 10 T64 6
valid_sources[0x17] 2660 1 T29 1 T194 1 T32 1
valid_sources[0x18] 2871 1 T64 4 T84 1 T69 20
valid_sources[0x19] 2740 1 T5 2 T150 1 T11 1
valid_sources[0x1a] 2923 1 T12 1 T157 1 T194 2
valid_sources[0x1b] 3127 1 T150 1 T194 2 T67 7
valid_sources[0x1c] 2901 1 T153 2 T32 2 T67 2
valid_sources[0x1d] 2634 1 T11 1 T191 1 T189 1
valid_sources[0x1e] 2908 1 T25 2 T191 1 T189 1
valid_sources[0x1f] 2884 1 T150 1 T32 2 T64 9
valid_sources[0x20] 2823 1 T127 2 T67 2 T64 6
valid_sources[0x21] 2868 1 T12 1 T162 2 T189 1
valid_sources[0x22] 2660 1 T150 1 T194 2 T32 3
valid_sources[0x23] 2852 1 T127 1 T13 1 T153 1
valid_sources[0x24] 2655 1 T150 2 T191 1 T67 5
valid_sources[0x25] 3102 1 T40 20 T36 6 T23 1
valid_sources[0x26] 2746 1 T6 17 T16 1 T137 6
valid_sources[0x27] 3003 1 T64 7 T84 2 T69 29
valid_sources[0x28] 2885 1 T158 1 T191 1 T21 3
valid_sources[0x29] 3262 1 T167 1 T67 1 T64 5
valid_sources[0x2a] 3119 1 T16 1 T160 4 T67 11
valid_sources[0x2b] 3478 1 T13 2 T191 1 T192 1
valid_sources[0x2c] 2871 1 T193 1 T64 4 T68 1
valid_sources[0x2d] 3167 1 T191 1 T67 8 T64 9
valid_sources[0x2e] 2808 1 T5 1 T167 1 T150 1
valid_sources[0x2f] 3119 1 T12 1 T169 14 T11 1
valid_sources[0x30] 3201 1 T5 4 T127 3 T191 1
valid_sources[0x31] 2905 1 T25 1 T14 1 T68 3
valid_sources[0x32] 2861 1 T5 1 T190 1 T33 1
valid_sources[0x33] 2799 1 T10 1 T21 2 T189 1
valid_sources[0x34] 2904 1 T11 1 T191 1 T67 7
valid_sources[0x35] 3240 1 T29 1 T191 1 T33 1
valid_sources[0x36] 3563 1 T67 2 T64 20 T68 2
valid_sources[0x37] 2962 1 T156 2 T150 1 T32 1
valid_sources[0x38] 3779 1 T25 2 T34 1 T127 2
valid_sources[0x39] 3195 1 T151 8 T195 4 T32 1
valid_sources[0x3a] 3070 1 T25 1 T32 1 T67 4
valid_sources[0x3b] 3205 1 T12 1 T196 2 T190 1
valid_sources[0x3c] 2862 1 T158 1 T160 1 T195 1
valid_sources[0x3d] 2674 1 T25 1 T34 4 T127 3
valid_sources[0x3e] 3283 1 T197 1 T67 2 T64 10
valid_sources[0x3f] 3109 1 T36 1 T11 1 T33 1
valid_sources[0x40] 3246 1 T190 1 T194 1 T32 1
valid_sources[0x41] 2716 1 T31 1 T16 1 T67 2
valid_sources[0x42] 2981 1 T64 3 T68 1 T69 36
valid_sources[0x43] 3231 1 T32 1 T67 9 T64 2
valid_sources[0x44] 3398 1 T12 1 T64 1 T68 1
valid_sources[0x45] 2615 1 T35 11 T191 1 T194 1
valid_sources[0x46] 2858 1 T55 1 T12 1 T16 1
valid_sources[0x47] 2760 1 T7 4 T13 1 T67 4
valid_sources[0x48] 2801 1 T29 1 T64 10 T68 2
valid_sources[0x49] 2906 1 T36 2 T16 1 T191 1
valid_sources[0x4a] 3093 1 T29 1 T32 1 T67 2
valid_sources[0x4b] 2794 1 T16 1 T154 6 T150 1
valid_sources[0x4c] 3287 1 T196 7 T150 1 T194 3
valid_sources[0x4d] 2772 1 T191 1 T64 12 T65 66
valid_sources[0x4e] 2947 1 T25 1 T67 1 T64 13
valid_sources[0x4f] 2868 1 T25 2 T13 1 T194 1
valid_sources[0x50] 10111 1 T5 1 T36 1 T193 1
valid_sources[0x51] 2952 1 T16 1 T150 1 T153 1
valid_sources[0x52] 2787 1 T32 2 T67 1 T64 5
valid_sources[0x53] 3188 1 T67 5 T64 11 T68 2
valid_sources[0x54] 2628 1 T29 1 T137 1 T191 1
valid_sources[0x55] 5842 1 T67 2 T64 7 T68 1
valid_sources[0x56] 3166 1 T16 1 T32 3 T67 1
valid_sources[0x57] 2655 1 T150 1 T194 1 T131 1
valid_sources[0x58] 2848 1 T22 10 T32 1 T67 2
valid_sources[0x59] 3015 1 T16 1 T157 1 T167 2
valid_sources[0x5a] 3250 1 T12 3 T10 3 T11 1
valid_sources[0x5b] 2895 1 T150 1 T67 1 T64 3
valid_sources[0x5c] 2872 1 T64 10 T68 3 T84 2
valid_sources[0x5d] 2680 1 T12 1 T150 1 T64 7
valid_sources[0x5e] 2936 1 T190 1 T194 1 T33 1
valid_sources[0x5f] 3185 1 T150 2 T67 1 T64 8
valid_sources[0x60] 2897 1 T32 2 T33 1 T67 1
valid_sources[0x61] 3073 1 T23 1 T198 2 T67 6
valid_sources[0x62] 2894 1 T5 1 T191 1 T194 2
valid_sources[0x63] 3041 1 T150 1 T32 2 T67 3
valid_sources[0x64] 6200 1 T7 2 T152 11 T189 1
valid_sources[0x65] 2644 1 T190 1 T153 1 T67 1
valid_sources[0x66] 3251 1 T199 1 T191 1 T194 1
valid_sources[0x67] 3079 1 T191 2 T67 1 T64 12
valid_sources[0x68] 3198 1 T196 6 T162 1 T33 2
valid_sources[0x69] 2967 1 T29 1 T10 1 T150 1
valid_sources[0x6a] 2848 1 T34 1 T192 1 T32 2
valid_sources[0x6b] 2710 1 T29 1 T36 2 T194 1
valid_sources[0x6c] 2783 1 T60 3 T64 8 T69 23
valid_sources[0x6d] 3092 1 T12 1 T13 1 T19 1
valid_sources[0x6e] 2825 1 T32 1 T67 6 T64 4
valid_sources[0x6f] 2883 1 T196 1 T200 1 T32 1
valid_sources[0x70] 3563 1 T150 1 T191 2 T67 2
valid_sources[0x71] 2814 1 T16 1 T150 1 T67 1
valid_sources[0x72] 3019 1 T67 1 T64 13 T68 2
valid_sources[0x73] 2903 1 T13 1 T194 1 T67 2
valid_sources[0x74] 2987 1 T191 1 T189 1 T32 1
valid_sources[0x75] 2799 1 T13 2 T190 1 T67 1
valid_sources[0x76] 3511 1 T190 1 T67 2 T64 17
valid_sources[0x77] 2803 1 T36 5 T162 1 T67 10
valid_sources[0x78] 3055 1 T16 1 T13 1 T64 7
valid_sources[0x79] 2817 1 T16 1 T150 1 T200 1
valid_sources[0x7a] 3246 1 T36 4 T190 1 T64 6
valid_sources[0x7b] 2921 1 T29 2 T64 1 T68 2
valid_sources[0x7c] 2718 1 T32 1 T67 5 T64 3
valid_sources[0x7d] 3094 1 T157 1 T67 8 T64 6
valid_sources[0x7e] 3315 1 T34 1 T29 1 T12 1
valid_sources[0x7f] 2973 1 T10 1 T64 9 T68 1
valid_sources[0x80] 3237 1 T12 1 T64 4 T68 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 296601 1 T4 1 T7 3 T6 1
values[0x0] all_enables biggest_size 133275 1 T4 1 T5 3 T6 5
values[0x1] all_enables biggest_size 132766 1 T5 1 T6 1 T25 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5079 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21121 1 T8 1 T1 1 T2 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 10171 1 T67 94 T64 51 T70 3
values[0x0] 7866 1 T8 1 T1 1 T2 10
values[0x1] 8163 1 T2 13 T3 3 T9 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3835 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22365 1 T8 1 T1 1 T2 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 129 1 T13 1 T201 1 T141 2
valid_sources[0x01] 54 1 T163 1 T20 1 T57 1
valid_sources[0x02] 89 1 T202 1 T84 1 T46 3
valid_sources[0x03] 64 1 T203 6 T67 2 T68 4
valid_sources[0x04] 84 1 T204 1 T142 1 T205 2
valid_sources[0x05] 65 1 T84 2 T86 2 T46 2
valid_sources[0x06] 81 1 T206 1 T68 2 T84 2
valid_sources[0x07] 100 1 T204 1 T207 1 T208 1
valid_sources[0x08] 122 1 T1 1 T73 1 T31 4
valid_sources[0x09] 85 1 T204 1 T209 1 T68 1
valid_sources[0x0a] 103 1 T162 1 T68 1 T84 2
valid_sources[0x0b] 82 1 T7 1 T5 2 T210 1
valid_sources[0x0c] 98 1 T76 1 T211 7 T189 1
valid_sources[0x0d] 71 1 T68 1 T65 1 T69 1
valid_sources[0x0e] 135 1 T3 1 T28 9 T212 6
valid_sources[0x0f] 108 1 T213 1 T49 1 T93 4
valid_sources[0x10] 262 1 T202 2 T166 6 T214 3
valid_sources[0x11] 85 1 T213 1 T215 2 T59 1
valid_sources[0x12] 89 1 T9 3 T68 4 T84 1
valid_sources[0x13] 894 1 T52 1 T216 5 T217 2
valid_sources[0x14] 66 1 T84 1 T46 2 T87 2
valid_sources[0x15] 85 1 T169 1 T217 1 T68 11
valid_sources[0x16] 109 1 T11 1 T218 1 T134 1
valid_sources[0x17] 97 1 T82 1 T215 1 T84 2
valid_sources[0x18] 83 1 T76 1 T219 1 T210 3
valid_sources[0x19] 153 1 T142 1 T220 1 T67 8
valid_sources[0x1a] 74 1 T221 1 T150 1 T18 1
valid_sources[0x1b] 102 1 T201 1 T152 1 T222 1
valid_sources[0x1c] 94 1 T154 3 T84 3 T69 1
valid_sources[0x1d] 133 1 T19 1 T61 1 T67 49
valid_sources[0x1e] 100 1 T223 1 T68 2 T84 1
valid_sources[0x1f] 71 1 T10 1 T224 1 T84 3
valid_sources[0x20] 71 1 T76 1 T225 1 T84 2
valid_sources[0x21] 127 1 T146 1 T68 4 T84 1
valid_sources[0x22] 83 1 T3 1 T69 3 T46 3
valid_sources[0x23] 65 1 T4 1 T226 1 T68 1
valid_sources[0x24] 80 1 T84 2 T87 2 T88 2
valid_sources[0x25] 136 1 T227 1 T228 1 T195 8
valid_sources[0x26] 47 1 T84 2 T66 4 T86 1
valid_sources[0x27] 81 1 T84 3 T69 1 T93 1
valid_sources[0x28] 78 1 T229 1 T230 1 T84 2
valid_sources[0x29] 63 1 T68 1 T84 2 T93 1
valid_sources[0x2a] 61 1 T23 1 T137 1 T68 3
valid_sources[0x2b] 66 1 T136 1 T231 2 T68 4
valid_sources[0x2c] 102 1 T148 1 T232 1 T153 1
valid_sources[0x2d] 64 1 T233 1 T225 2 T68 7
valid_sources[0x2e] 91 1 T163 1 T153 1 T65 1
valid_sources[0x2f] 60 1 T55 1 T223 1 T58 1
valid_sources[0x30] 136 1 T234 1 T213 1 T205 1
valid_sources[0x31] 96 1 T68 9 T84 2 T65 1
valid_sources[0x32] 149 1 T235 16 T68 5 T84 3
valid_sources[0x33] 84 1 T68 2 T69 1 T86 1
valid_sources[0x34] 94 1 T12 1 T213 1 T155 4
valid_sources[0x35] 106 1 T3 1 T142 1 T194 9
valid_sources[0x36] 69 1 T24 1 T229 1 T150 1
valid_sources[0x37] 90 1 T227 1 T190 5 T236 17
valid_sources[0x38] 194 1 T5 4 T40 2 T167 1
valid_sources[0x39] 80 1 T90 2 T84 2 T66 1
valid_sources[0x3a] 88 1 T160 7 T237 1 T84 1
valid_sources[0x3b] 72 1 T238 1 T164 1 T11 1
valid_sources[0x3c] 88 1 T84 1 T65 1 T93 5
valid_sources[0x3d] 103 1 T156 5 T158 2 T201 1
valid_sources[0x3e] 92 1 T68 13 T84 2 T87 3
valid_sources[0x3f] 104 1 T201 1 T217 1 T193 1
valid_sources[0x40] 63 1 T84 2 T69 2 T66 1
valid_sources[0x41] 65 1 T153 1 T239 1 T193 1
valid_sources[0x42] 102 1 T28 2 T207 1 T164 2
valid_sources[0x43] 136 1 T51 2 T165 1 T161 1
valid_sources[0x44] 91 1 T150 1 T240 4 T241 1
valid_sources[0x45] 119 1 T242 1 T243 1 T225 1
valid_sources[0x46] 91 1 T73 1 T142 1 T244 2
valid_sources[0x47] 88 1 T245 1 T246 1 T64 1
valid_sources[0x48] 147 1 T40 2 T247 1 T174 1
valid_sources[0x49] 70 1 T248 1 T84 3 T93 3
valid_sources[0x4a] 94 1 T218 1 T65 2 T46 3
valid_sources[0x4b] 108 1 T68 3 T65 1 T86 1
valid_sources[0x4c] 88 1 T68 4 T84 2 T65 2
valid_sources[0x4d] 86 1 T12 1 T163 1 T158 1
valid_sources[0x4e] 61 1 T39 1 T150 1 T84 1
valid_sources[0x4f] 141 1 T29 6 T84 1 T66 1
valid_sources[0x50] 102 1 T233 2 T238 1 T68 2
valid_sources[0x51] 90 1 T34 5 T213 1 T233 1
valid_sources[0x52] 84 1 T154 2 T152 1 T223 1
valid_sources[0x53] 86 1 T249 1 T168 6 T32 1
valid_sources[0x54] 93 1 T12 2 T250 1 T30 1
valid_sources[0x55] 99 1 T68 4 T84 3 T65 3
valid_sources[0x56] 144 1 T207 1 T251 3 T151 1
valid_sources[0x57] 97 1 T130 8 T68 8 T84 1
valid_sources[0x58] 82 1 T84 1 T69 2 T46 4
valid_sources[0x59] 108 1 T210 1 T157 1 T84 1
valid_sources[0x5a] 76 1 T244 2 T84 2 T91 1
valid_sources[0x5b] 63 1 T173 1 T227 1 T84 1
valid_sources[0x5c] 99 1 T9 1 T234 1 T245 1
valid_sources[0x5d] 191 1 T222 1 T64 86 T68 6
valid_sources[0x5e] 135 1 T3 2 T240 2 T67 5
valid_sources[0x5f] 89 1 T23 1 T68 1 T84 2
valid_sources[0x60] 121 1 T67 33 T68 3 T69 2
valid_sources[0x61] 77 1 T156 1 T252 4 T253 1
valid_sources[0x62] 105 1 T31 3 T233 3 T223 1
valid_sources[0x63] 75 1 T142 1 T147 1 T67 5
valid_sources[0x64] 67 1 T254 1 T68 1 T84 1
valid_sources[0x65] 85 1 T219 1 T138 8 T84 3
valid_sources[0x66] 103 1 T84 4 T69 3 T93 6
valid_sources[0x67] 169 1 T67 52 T84 1 T65 1
valid_sources[0x68] 84 1 T234 1 T242 1 T68 1
valid_sources[0x69] 110 1 T15 3 T48 1 T67 14
valid_sources[0x6a] 112 1 T54 1 T68 1 T84 1
valid_sources[0x6b] 73 1 T169 1 T212 1 T68 1
valid_sources[0x6c] 77 1 T219 1 T157 1 T68 4
valid_sources[0x6d] 56 1 T158 3 T84 3 T87 1
valid_sources[0x6e] 102 1 T2 1 T152 1 T245 1
valid_sources[0x6f] 262 1 T210 1 T84 2 T65 1
valid_sources[0x70] 53 1 T232 1 T68 2 T84 1
valid_sources[0x71] 86 1 T219 1 T201 1 T84 1
valid_sources[0x72] 168 1 T2 4 T209 1 T242 1
valid_sources[0x73] 78 1 T133 1 T84 5 T65 1
valid_sources[0x74] 62 1 T204 1 T143 1 T69 1
valid_sources[0x75] 60 1 T230 2 T84 1 T65 1
valid_sources[0x76] 186 1 T53 1 T243 3 T189 1
valid_sources[0x77] 111 1 T217 1 T68 4 T84 3
valid_sources[0x78] 93 1 T219 1 T242 1 T67 26
valid_sources[0x79] 95 1 T163 2 T192 8 T68 3
valid_sources[0x7a] 78 1 T159 1 T67 3 T84 3
valid_sources[0x7b] 57 1 T54 1 T84 2 T87 3
valid_sources[0x7c] 116 1 T76 3 T201 1 T242 1
valid_sources[0x7d] 102 1 T255 1 T84 3 T93 7
valid_sources[0x7e] 61 1 T201 1 T150 1 T84 1
valid_sources[0x7f] 118 1 T232 2 T256 7 T68 2
valid_sources[0x80] 95 1 T202 2 T10 1 T242 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7029 1 T67 85 T64 45 T70 1
values[0x0] all_enables biggest_size 7130 1 T8 1 T1 1 T2 2
values[0x1] all_enables biggest_size 6962 1 T2 5 T9 2 T15 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%