Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	266040	1		T4	12		T7	6		T5	14
full_word	564591	1		T4	2		T7	3		T5	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	830361	1		T4	14		T7	9		T5	18
auto[TlIntgErrCmd]	93	1		T85	2		T86	13		T126	4
auto[TlIntgErrData]	83	1		T85	1		T86	4		T126	5
auto[TlIntgErrBoth]	94	1		T85	7		T86	3		T126	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	506740	1		T4	6		T7	8		T6	1
auto[1]	323891	1		T4	8		T7	1		T5	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	209812	1		T4	5		T7	5		T25	1
auto[TlIntgErrNone]	partial	auto[1]	55981	1		T4	7		T7	1		T5	14
auto[TlIntgErrNone]	full_word	auto[0]	296812	1		T4	1		T7	3		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	267756	1		T4	1		T5	4		T6	6
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T85	2		T86	6		T126	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T86	4		T126	2		T123	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T86	2		T125	1		T183	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T86	1		T181	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T85	1		T86	1		T126	1
auto[TlIntgErrData]	partial	auto[1]	41	1		T86	3		T126	4		T123	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T125	1		T180	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T184	1		T185	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T85	1		T86	1		T123	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T85	5		T86	2		T126	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T183	1		T186	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T85	1		T187	1		T180	1