Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.87	100.00	59.57	92.28		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119559085	16267	0	0
late_debug_enable_rd_A	119559085	3961	0	0
late_debug_enable_regwen_rd_A	119559085	3839	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119559085	16267	0	0
T46	198032	210	0	0
T64	19584	41	0	0
T65	6572	34	0	0
T66	26590	6	0	0
T67	9494	622	0	0
T68	25998	622	0	0
T84	17127	533	0	0
T85	79295	1	0	0
T86	314226	3	0	0
T87	6442	548	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119559085	3961	0	0
T47	252287	241	0	0
T70	7966	4	0	0
T85	79295	43	0	0
T94	42377	36	0	0
T103	56655	31	0	0
T113	7367	5	0	0
T121	46191	44	0	0
T123	62891	17	0	0
T124	23101	4	0	0
T125	87759	28	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119559085	3839	0	0
T47	252287	220	0	0
T70	7966	1	0	0
T85	79295	51	0	0
T94	42377	87	0	0
T98	9307	3	0	0
T103	56655	13	0	0
T112	337540	1023	0	0
T123	62891	25	0	0
T124	23101	17	0	0
T125	87759	18	0	0