Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.87	100.00	59.57	92.28		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	46207049	4900912	0	0
MemTLResponseWithoutDebugIsError_A	46207049	1	0	0
NdmResetAckNeedsDebug_A	46207049	0	0	0
SbaTLRequestNeedsDebug_A	46207049	10490	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46207049	4900912	0	0
T4	15604	6771	0	0
T5	439144	90047	0	0
T6	0	182583	0	0
T7	23302	18334	0	0
T25	0	65163	0	0
T27	358261	0	0	0
T29	0	121150	0	0
T31	0	126689	0	0
T34	0	2354	0	0
T40	0	71428	0	0
T41	1656	0	0	0
T51	49952	0	0	0
T52	812966	0	0	0
T53	520702	0	0	0
T54	1742	0	0	0
T55	0	3172	0	0
T56	530695	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46207049	1	0	0
T33	5096	0	0	0
T57	4424	1	0	0
T58	437482	0	0	0
T59	415200	0	0	0
T60	39027	0	0	0
T61	14110	0	0	0
T62	420817	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46207049	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46207049	10490	0	0
T1	207778	63	0	0
T2	1689	0	0	0
T3	2382	0	0	0
T4	15604	0	0	0
T7	23302	0	0	0
T9	599390	7	0	0
T15	266101	134	0	0
T24	633010	15	0	0
T26	133436	0	0	0
T27	0	357	0	0
T39	145961	61	0	0
T51	0	53	0	0
T52	0	63	0	0
T53	0	34	0	0
T56	0	30	0	0