Unified Coverage Report :: Module :: dmi_jtag_tap

Module : dmi_jtag_tap

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.75	100.00	100.00		68.42	98.57

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap.i_dmi_jtag_tap	91.75	100.00	100.00		68.42	98.57

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.75	100.00	100.00		68.42	98.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.58	100.00	90.91		68.42	98.57	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.48	94.32	90.57		66.67	82.35		dap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_tck_inv	85.19	100.00	55.56				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : dmi_jtag_tap

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
ALWAYS	79	11	11	100.00
ALWAYS	105	5	5	100.00
ALWAYS	127	15	15	100.00
ALWAYS	151	10	10	100.00
ALWAYS	172	6	6	100.00
ALWAYS	201	5	5	100.00
ALWAYS	215	31	31	100.00
ALWAYS	302	7	7	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
80	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
89	1	1
			MISSING_ELSE
93	1	1
94	1	1
			MISSING_ELSE
97	1	1
99	1	1
100	1	1
			MISSING_ELSE
105	1	1
106	1	1
107	1	1
109	1	1
110	1	1
127	1	1
128	1	1
130	1	1
131	2	2
			MISSING_ELSE
132	2	2
			MISSING_ELSE
			MISSING_ELSE
135	1	1
136	2	2
			MISSING_ELSE
137	2	2
			MISSING_ELSE
			MISSING_ELSE
140	1	1
142	1	1
143	1	1
			MISSING_ELSE
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
172	1	1
173	1	1
176	1	1
177	1	1
178	1	1
179	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
215	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
224	1	1
226	1	1
228	1	1
229	1	1
232	1	1
236	1	1
239	1	1
240	1	1
243	1	1
244	1	1
247	1	1
250	1	1
253	1	1
256	1	1
257	1	1
261	1	1
268	1	1
269	1	1
276	1	1
277	1	1
280	1	1
284	1	1
287	1	1
294	1	1
295	1	1
302	1	1
303	1	1
304	1	1
305	1	1
307	1	1
308	1	1
309	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1

---

Cond Coverage for Module : dmi_jtag_tap

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       206
 EXPRESSION (shift_ir | shift_dr)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T2
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2

 LINE       228
 EXPRESSION (tms_i ? TestLogicReset : RunTestIdle)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T45,T46,T47

 LINE       232
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       236
 EXPRESSION (tms_i ? SelectIrScan : CaptureDr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       240
 EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T45,T46,T47

 LINE       244
 EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       247
 EXPRESSION (tms_i ? UpdateDr : PauseDr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       250
 EXPRESSION (tms_i ? Exit2Dr : PauseDr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T9

 LINE       253
 EXPRESSION (tms_i ? UpdateDr : ShiftDr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T9

 LINE       257
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       261
 EXPRESSION (tms_i ? TestLogicReset : CaptureIr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       269
 EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T34,T29,T12

 LINE       277
 EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       280
 EXPRESSION (tms_i ? UpdateIr : PauseIr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       284
 EXPRESSION (tms_i ? Exit2Ir : PauseIr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       287
 EXPRESSION (tms_i ? UpdateIr : ShiftIr)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

 LINE       295
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--

-1-	Status	Tests
0	Covered	T8,T1,T2
1	Covered	T8,T1,T2

---

FSM Coverage for Module : dmi_jtag_tap

Summary for FSM :: tap_state_q

	Total	Covered	Percent
States	16	16	100.00	(Not included in score)
Transitions	38	26	68.42
Sequences	0	0

State, Transition and Sequence Details for FSM :: tap_state_q

---

states	Line No.	Covered	Tests
CaptureDr	236	Covered	T8,T1,T2
CaptureIr	261	Covered	T8,T1,T2
Exit1Dr	240	Covered	T8,T1,T2
Exit1Ir	269	Covered	T8,T1,T2
Exit2Dr	250	Covered	T8,T1,T9
Exit2Ir	284	Covered	T8,T1,T2
PauseDr	247	Covered	T8,T1,T9
PauseIr	280	Covered	T8,T1,T2
RunTestIdle	303	Covered	T8,T1,T2
SelectDrScan	232	Covered	T8,T1,T2
SelectIrScan	236	Covered	T8,T1,T2
ShiftDr	240	Covered	T8,T1,T2
ShiftIr	269	Covered	T8,T1,T2
TestLogicReset	228	Covered	T45,T46,T47
UpdateDr	247	Covered	T8,T1,T2
UpdateIr	280	Covered	T8,T1,T2

transitions	Line No.	Covered	Tests
CaptureDr->Exit1Dr	240	Covered	T45,T46,T47
CaptureDr->RunTestIdle	303	Not Covered
CaptureDr->ShiftDr	240	Covered	T8,T1,T2
CaptureIr->Exit1Ir	269	Covered	T34,T29,T12
CaptureIr->RunTestIdle	303	Not Covered
CaptureIr->ShiftIr	269	Covered	T8,T1,T2
Exit1Dr->PauseDr	247	Covered	T8,T1,T9
Exit1Dr->RunTestIdle	303	Not Covered
Exit1Dr->UpdateDr	247	Covered	T8,T1,T2
Exit1Ir->PauseIr	280	Covered	T8,T1,T2
Exit1Ir->RunTestIdle	303	Not Covered
Exit1Ir->UpdateIr	280	Covered	T8,T2,T3
Exit2Dr->RunTestIdle	303	Not Covered
Exit2Dr->ShiftDr	253	Covered	T8,T1,T9
Exit2Dr->UpdateDr	253	Covered	T1,T9,T26
Exit2Ir->RunTestIdle	303	Not Covered
Exit2Ir->ShiftIr	287	Covered	T8,T2,T3
Exit2Ir->UpdateIr	287	Covered	T1,T26,T52
PauseDr->Exit2Dr	250	Covered	T8,T1,T9
PauseDr->RunTestIdle	303	Not Covered
PauseIr->Exit2Ir	284	Covered	T8,T1,T2
PauseIr->RunTestIdle	303	Not Covered
RunTestIdle->SelectDrScan	232	Covered	T8,T1,T2
SelectDrScan->CaptureDr	236	Covered	T8,T1,T2
SelectDrScan->RunTestIdle	303	Not Covered
SelectDrScan->SelectIrScan	236	Covered	T8,T1,T2
SelectIrScan->CaptureIr	261	Covered	T8,T1,T2
SelectIrScan->RunTestIdle	303	Not Covered
SelectIrScan->TestLogicReset	261	Covered	T45,T46,T47
ShiftDr->Exit1Dr	244	Covered	T8,T1,T2
ShiftDr->RunTestIdle	303	Not Covered
ShiftIr->Exit1Ir	277	Covered	T8,T1,T2
ShiftIr->RunTestIdle	303	Not Covered
TestLogicReset->RunTestIdle	303	Covered	T45,T46,T47
UpdateDr->RunTestIdle	303	Covered	T8,T1,T2
UpdateDr->SelectDrScan	257	Covered	T45,T46,T47
UpdateIr->RunTestIdle	303	Covered	T8,T1,T2
UpdateIr->SelectDrScan	295	Covered	T45,T46,T47

---

Branch Coverage for Module : dmi_jtag_tap

	Line No.	Total	Covered	Percent
Branches		70	69	98.57
IF	83	2	2	100.00
IF	88	2	2	100.00
IF	93	2	2	100.00
IF	97	2	2	100.00
IF	105	2	2	100.00
IF	130	5	5	100.00
IF	135	5	5	100.00
IF	140	2	2	100.00
CASE	155	6	6	100.00
IF	172	5	5	100.00
IF	201	2	2	100.00
CASE	226	33	32	96.97
IF	302	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	if (shift_ir)

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	88	if (capture_ir)

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	93	if (update_ir)

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	97	if (test_logic_reset)

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	105	if ((!trst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	130	if (capture_dr)
-2-:	131	if (idcode_select)
-3-:	132	if (bypass_select)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T8,T1,T2
1	0	-	Covered	T8,T1,T2
1	-	1	Covered	T8,T1,T2
1	-	0	Covered	T8,T1,T2
0	-	-	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	135	if (shift_dr)
-2-:	136	if (idcode_select)
-3-:	137	if (bypass_select)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T8,T1,T2
1	0	-	Covered	T8,T1,T2
1	-	1	Covered	T8,T1,T2
1	-	0	Covered	T8,T1,T2
0	-	-	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	140	if (test_logic_reset)

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	155	case (jtag_ir_q)

Branches:

-1-	Status	Tests
BYPASS0	Covered	T45,T79,T80
IDCODE	Covered	T8,T1,T2
DTMCSR	Covered	T5,T6,T25
DMIACCESS	Covered	T8,T1,T2
BYPASS1	Covered	T79,T80,T81
default	Covered	T34,T29,T12

	LineNo.	Expression
-1-:	172	if (shift_ir)
-2-:	176	case (jtag_ir_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T1,T2
0	IDCODE	Covered	T8,T1,T2
0	DTMCSR	Covered	T5,T6,T25
0	DMIACCESS	Covered	T8,T1,T2
0	default	Covered	T34,T29,T12

	LineNo.	Expression
-1-:	201	if ((!trst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2

	LineNo.	Expression
-1-:	226	case (tap_state_q)
-2-:	228	(tms_i) ? 
-3-:	232	(tms_i) ? 
-4-:	236	(tms_i) ? 
-5-:	240	(tms_i) ? 
-6-:	244	(tms_i) ? 
-7-:	247	(tms_i) ? 
-8-:	250	(tms_i) ? 
-9-:	253	(tms_i) ? 
-10-:	257	(tms_i) ? 
-11-:	261	(tms_i) ? 
-12-:	269	(tms_i) ? 
-13-:	277	(tms_i) ? 
-14-:	280	(tms_i) ? 
-15-:	284	(tms_i) ? 
-16-:	287	(tms_i) ? 
-17-:	295	(tms_i) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
TestLogicReset	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T46,T47
TestLogicReset	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
RunTestIdle	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
RunTestIdle	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
SelectDrScan	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
SelectDrScan	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
CaptureDr	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T46,T47
CaptureDr	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
ShiftDr	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
ShiftDr	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
Exit1Dr	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
Exit1Dr	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
PauseDr	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T9
PauseDr	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
Exit2Dr	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T8,T1,T9
Exit2Dr	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T8,T1,T2
UpdateDr	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T8,T1,T2
UpdateDr	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T1,T2
SelectIrScan	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T1,T2
SelectIrScan	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T8,T1,T2
CaptureIr	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T34,T29,T12
CaptureIr	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T1,T2
ShiftIr	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T1,T2
ShiftIr	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T1,T2
Exit1Ir	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T1,T2
Exit1Ir	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T8,T1,T2
PauseIr	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T8,T1,T2
PauseIr	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T8,T1,T2
Exit2Ir	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T1,T2
Exit2Ir	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T1,T2
UpdateIr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T1,T2
UpdateIr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T1,T2
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	302	if ((!trst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T1,T2
0	Covered	T8,T1,T2