Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T1,T2
01CoveredT8,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT8,T1,T2
11CoveredT8,T1,T2

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8723564 8722220 0 0
selKnown1 52490102 52488758 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8723564 8722220 0 0
T1 14637 14635 0 0
T2 770 768 0 0
T3 521 519 0 0
T4 5428 5424 0 0
T5 0 18 0 0
T6 0 24 0 0
T7 2 0 0 0
T8 2409 2407 0 0
T9 14837 14833 0 0
T15 27479 27475 0 0
T24 32517 32513 0 0
T26 5121 5117 0 0
T27 8 6 0 0
T28 0 24 0 0
T39 15536 15532 0 0
T42 0 20 0 0
T51 0 8 0 0
T52 0 8 0 0
T53 2 0 0 0
T54 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 52490102 52488758 0 0
T1 215096 215094 0 0
T2 2074 2072 0 0
T3 2642 2640 0 0
T4 18319 18315 0 0
T5 0 8 0 0
T6 0 8 0 0
T7 2 0 0 0
T8 9088 9086 0 0
T9 606812 606808 0 0
T15 279843 279839 0 0
T24 649275 649271 0 0
T26 135997 135993 0 0
T27 8 6 0 0
T28 0 24 0 0
T39 153730 153726 0 0
T42 0 20 0 0
T51 0 8 0 0
T52 0 8 0 0
T53 2 0 0 0
T54 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T1,T2
01CoveredT8,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT8,T1,T2
11CoveredT8,T1,T2

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2439992 2439765 0 0
selKnown1 46207049 46206822 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2439992 2439765 0 0
T1 7318 7317 0 0
T2 385 384 0 0
T3 260 259 0 0
T4 2713 2712 0 0
T8 1204 1203 0 0
T9 7414 7413 0 0
T15 13736 13735 0 0
T24 16251 16250 0 0
T26 2559 2558 0 0
T39 7767 7766 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 46207049 46206822 0 0
T1 207778 207777 0 0
T2 1689 1688 0 0
T3 2382 2381 0 0
T4 15604 15603 0 0
T8 7884 7883 0 0
T9 599390 599389 0 0
T15 266101 266100 0 0
T24 633010 633009 0 0
T26 133436 133435 0 0
T39 145961 145960 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T1,T2
01CoveredT8,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT8,T1,T2
11CoveredT8,T1,T2

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 673 446 0 0
selKnown1 642 415 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 673 446 0 0
T4 1 0 0 0
T5 0 6 0 0
T6 0 7 0 0
T7 1 0 0 0
T9 4 3 0 0
T15 3 2 0 0
T24 7 6 0 0
T26 1 0 0 0
T27 4 3 0 0
T28 0 12 0 0
T39 1 0 0 0
T42 0 10 0 0
T51 0 4 0 0
T52 0 4 0 0
T53 1 0 0 0
T54 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 642 415 0 0
T4 1 0 0 0
T5 0 4 0 0
T6 0 4 0 0
T7 1 0 0 0
T9 4 3 0 0
T15 3 2 0 0
T24 7 6 0 0
T26 1 0 0 0
T27 4 3 0 0
T28 0 12 0 0
T39 1 0 0 0
T42 0 10 0 0
T51 0 4 0 0
T52 0 4 0 0
T53 1 0 0 0
T54 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T1,T2
01CoveredT8,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT8,T1,T2
11CoveredT8,T1,T2

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6280958 6280513 0 0
selKnown1 6280759 6280314 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6280958 6280513 0 0
T1 7319 7318 0 0
T2 385 384 0 0
T3 261 260 0 0
T4 2713 2712 0 0
T8 1205 1204 0 0
T9 7415 7414 0 0
T15 13737 13736 0 0
T24 16252 16251 0 0
T26 2560 2559 0 0
T39 7767 7766 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6280759 6280314 0 0
T1 7318 7317 0 0
T2 385 384 0 0
T3 260 259 0 0
T4 2713 2712 0 0
T8 1204 1203 0 0
T9 7414 7413 0 0
T15 13736 13735 0 0
T24 16251 16250 0 0
T26 2559 2558 0 0
T39 7767 7766 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T1,T2
01CoveredT8,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT8,T1,T2
11CoveredT8,T1,T2

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1941 1496 0 0
selKnown1 1652 1207 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1941 1496 0 0
T4 1 0 0 0
T5 0 12 0 0
T6 0 17 0 0
T7 1 0 0 0
T9 4 3 0 0
T15 3 2 0 0
T24 7 6 0 0
T26 1 0 0 0
T27 4 3 0 0
T28 0 12 0 0
T39 1 0 0 0
T42 0 10 0 0
T51 0 4 0 0
T52 0 4 0 0
T53 1 0 0 0
T54 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1652 1207 0 0
T4 1 0 0 0
T5 0 4 0 0
T6 0 4 0 0
T7 1 0 0 0
T9 4 3 0 0
T15 3 2 0 0
T24 7 6 0 0
T26 1 0 0 0
T27 4 3 0 0
T28 0 12 0 0
T39 1 0 0 0
T42 0 10 0 0
T51 0 4 0 0
T52 0 4 0 0
T53 1 0 0 0
T54 1 0 0 0

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