Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	219788	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	608303	1		T1	20		T4	2		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	518024	1		T1	12		T3	7		T5	7
values[0x0]	151762	1		T1	22		T4	6		T3	6
values[0x1]	158305	1		T1	12		T4	4		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166992	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	661099	1		T1	23		T4	4		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3339	1		T132	1		T32	1		T66	5
valid_sources[0x01]	3474	1		T137	2		T66	1		T61	35
valid_sources[0x02]	3210	1		T61	33		T67	6		T65	1
valid_sources[0x03]	3375	1		T6	1		T37	1		T61	34
valid_sources[0x04]	3482	1		T15	1		T32	1		T133	1
valid_sources[0x05]	3119	1		T20	1		T31	2		T61	35
valid_sources[0x06]	3136	1		T5	27		T27	2		T30	1
valid_sources[0x07]	3252	1		T18	3		T66	1		T61	34
valid_sources[0x08]	3052	1		T66	1		T64	1		T61	40
valid_sources[0x09]	3388	1		T27	1		T31	1		T32	1
valid_sources[0x0a]	3223	1		T20	1		T32	2		T66	3
valid_sources[0x0b]	2889	1		T66	1		T61	26		T67	45
valid_sources[0x0c]	2968	1		T15	1		T20	1		T32	2
valid_sources[0x0d]	3154	1		T66	2		T61	48		T67	15
valid_sources[0x0e]	3283	1		T27	1		T30	1		T31	5
valid_sources[0x0f]	3419	1		T8	1		T61	42		T67	31
valid_sources[0x10]	3511	1		T33	1		T31	2		T21	5
valid_sources[0x11]	3527	1		T20	1		T31	1		T32	1
valid_sources[0x12]	3155	1		T132	2		T20	1		T61	54
valid_sources[0x13]	3390	1		T20	1		T31	2		T64	5
valid_sources[0x14]	2894	1		T134	4		T66	2		T61	44
valid_sources[0x15]	2943	1		T30	1		T61	32		T67	10
valid_sources[0x16]	2851	1		T27	1		T132	1		T31	1
valid_sources[0x17]	2917	1		T7	1		T182	1		T132	1
valid_sources[0x18]	3084	1		T20	1		T36	1		T37	1
valid_sources[0x19]	4825	1		T132	1		T141	1		T61	58
valid_sources[0x1a]	3682	1		T8	1		T183	1		T66	1
valid_sources[0x1b]	2926	1		T20	1		T31	1		T66	4
valid_sources[0x1c]	3357	1		T52	15		T31	2		T184	1
valid_sources[0x1d]	3106	1		T18	1		T66	7		T61	40
valid_sources[0x1e]	3172	1		T18	1		T66	2		T61	50
valid_sources[0x1f]	3301	1		T37	1		T66	9		T61	29
valid_sources[0x20]	3082	1		T27	1		T30	1		T132	1
valid_sources[0x21]	3298	1		T30	1		T66	5		T61	47
valid_sources[0x22]	2789	1		T1	46		T31	1		T61	28
valid_sources[0x23]	3046	1		T61	33		T67	15		T89	8
valid_sources[0x24]	3266	1		T184	1		T18	1		T61	34
valid_sources[0x25]	3060	1		T6	1		T51	1		T61	46
valid_sources[0x26]	2984	1		T6	1		T185	1		T19	3
valid_sources[0x27]	3420	1		T132	2		T31	3		T32	1
valid_sources[0x28]	3084	1		T15	1		T7	1		T61	29
valid_sources[0x29]	3342	1		T27	4		T20	1		T18	1
valid_sources[0x2a]	3035	1		T18	1		T61	41		T67	4
valid_sources[0x2b]	3165	1		T4	1		T30	1		T61	49
valid_sources[0x2c]	3102	1		T133	1		T66	3		T61	43
valid_sources[0x2d]	4568	1		T30	1		T132	3		T61	50
valid_sources[0x2e]	3196	1		T34	19		T31	4		T66	4
valid_sources[0x2f]	3125	1		T27	1		T132	1		T18	1
valid_sources[0x30]	3325	1		T20	1		T184	1		T66	2
valid_sources[0x31]	2893	1		T6	1		T8	1		T66	2
valid_sources[0x32]	3066	1		T31	2		T32	1		T66	2
valid_sources[0x33]	3819	1		T51	1		T132	1		T20	1
valid_sources[0x34]	3353	1		T18	1		T66	3		T61	52
valid_sources[0x35]	3357	1		T51	1		T132	1		T186	1
valid_sources[0x36]	3716	1		T31	1		T133	4		T66	9
valid_sources[0x37]	3373	1		T27	1		T32	1		T66	2
valid_sources[0x38]	3429	1		T27	1		T132	1		T66	3
valid_sources[0x39]	3189	1		T50	26		T66	2		T61	39
valid_sources[0x3a]	2986	1		T61	45		T67	5		T89	3
valid_sources[0x3b]	3914	1		T32	2		T66	1		T64	1
valid_sources[0x3c]	3389	1		T51	1		T17	1		T132	1
valid_sources[0x3d]	3242	1		T27	1		T31	1		T61	36
valid_sources[0x3e]	3182	1		T7	3		T32	1		T66	8
valid_sources[0x3f]	3366	1		T6	1		T61	46		T67	25
valid_sources[0x40]	2828	1		T32	1		T145	1		T61	40
valid_sources[0x41]	3029	1		T133	2		T61	57		T67	5
valid_sources[0x42]	3083	1		T32	1		T66	1		T61	37
valid_sources[0x43]	3643	1		T4	1		T66	4		T61	35
valid_sources[0x44]	3213	1		T20	1		T141	1		T66	3
valid_sources[0x45]	3223	1		T16	2		T132	3		T20	2
valid_sources[0x46]	3037	1		T30	1		T33	1		T132	1
valid_sources[0x47]	2888	1		T33	3		T66	3		T61	29
valid_sources[0x48]	2897	1		T4	1		T132	1		T31	1
valid_sources[0x49]	3140	1		T51	1		T66	1		T61	34
valid_sources[0x4a]	3095	1		T32	1		T66	5		T61	50
valid_sources[0x4b]	3181	1		T66	3		T61	15		T67	9
valid_sources[0x4c]	2871	1		T27	1		T51	1		T32	1
valid_sources[0x4d]	3510	1		T8	1		T31	1		T66	2
valid_sources[0x4e]	3516	1		T32	2		T66	1		T61	30
valid_sources[0x4f]	3023	1		T30	1		T132	2		T31	1
valid_sources[0x50]	3420	1		T31	2		T18	1		T141	1
valid_sources[0x51]	3233	1		T61	53		T67	5		T62	35
valid_sources[0x52]	3001	1		T66	2		T61	40		T67	7
valid_sources[0x53]	3833	1		T35	9		T61	59		T67	8
valid_sources[0x54]	3197	1		T66	1		T61	30		T67	10
valid_sources[0x55]	3296	1		T66	4		T61	48		T67	23
valid_sources[0x56]	3367	1		T20	1		T31	3		T32	1
valid_sources[0x57]	3280	1		T133	1		T66	1		T61	45
valid_sources[0x58]	3005	1		T20	1		T37	1		T66	3
valid_sources[0x59]	2967	1		T64	1		T61	63		T67	12
valid_sources[0x5a]	3490	1		T37	1		T64	2		T61	63
valid_sources[0x5b]	3488	1		T33	1		T20	1		T61	37
valid_sources[0x5c]	3541	1		T32	1		T133	1		T66	7
valid_sources[0x5d]	3105	1		T20	1		T31	4		T32	1
valid_sources[0x5e]	4184	1		T32	1		T66	12		T61	58
valid_sources[0x5f]	4746	1		T15	1		T61	39		T67	4
valid_sources[0x60]	3175	1		T8	1		T183	1		T37	1
valid_sources[0x61]	3164	1		T30	1		T6	1		T132	2
valid_sources[0x62]	3162	1		T17	1		T66	2		T61	62
valid_sources[0x63]	2911	1		T15	1		T187	1		T184	1
valid_sources[0x64]	2956	1		T182	1		T132	1		T32	1
valid_sources[0x65]	3309	1		T66	5		T61	26		T67	22
valid_sources[0x66]	4174	1		T132	1		T66	1		T61	35
valid_sources[0x67]	3129	1		T27	2		T66	2		T61	35
valid_sources[0x68]	3198	1		T64	1		T61	44		T67	8
valid_sources[0x69]	3289	1		T188	2		T189	28		T37	1
valid_sources[0x6a]	3076	1		T19	1		T8	2		T32	1
valid_sources[0x6b]	3652	1		T7	1		T132	1		T32	1
valid_sources[0x6c]	2983	1		T19	1		T20	1		T31	1
valid_sources[0x6d]	2857	1		T141	1		T61	24		T67	13
valid_sources[0x6e]	3333	1		T17	2		T32	1		T139	7
valid_sources[0x6f]	3050	1		T27	1		T66	1		T61	47
valid_sources[0x70]	3305	1		T30	1		T51	1		T132	1
valid_sources[0x71]	3083	1		T61	45		T67	9		T62	68
valid_sources[0x72]	3504	1		T32	1		T61	42		T67	23
valid_sources[0x73]	3537	1		T61	35		T67	2		T65	1
valid_sources[0x74]	3247	1		T8	1		T129	1		T66	4
valid_sources[0x75]	3104	1		T132	2		T66	4		T61	28
valid_sources[0x76]	3227	1		T141	3		T66	2		T61	32
valid_sources[0x77]	3200	1		T36	2		T61	48		T67	11
valid_sources[0x78]	2899	1		T182	1		T132	1		T32	1
valid_sources[0x79]	3118	1		T20	3		T66	10		T61	50
valid_sources[0x7a]	3578	1		T32	2		T136	6		T66	1
valid_sources[0x7b]	3594	1		T33	1		T132	1		T31	2
valid_sources[0x7c]	2896	1		T132	3		T190	2		T61	19
valid_sources[0x7d]	3399	1		T6	1		T66	4		T61	28
valid_sources[0x7e]	3121	1		T31	1		T61	54		T67	24
valid_sources[0x7f]	3407	1		T27	1		T22	1		T61	51
valid_sources[0x80]	3061	1		T132	1		T19	4		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

308947

1

T1

8

T3

3

T5

3

values[0x0]

all_enables

biggest_size

149588

1

T1

9

T4

2

T3

3

values[0x1]

all_enables

biggest_size

149768

1

T1

3

T15

1

T13

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4710	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	23390	1		T1	7		T4	1		T2	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9991	1		T66	3		T64	83		T61	69
values[0x0]	8807	1		T1	5		T4	1		T2	5
values[0x1]	9302	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3615	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	24485	1		T1	7		T4	1		T2	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	78	1		T25	1		T169	1		T65	1
valid_sources[0x01]	70	1		T165	1		T64	2		T65	1
valid_sources[0x02]	88	1		T133	1		T166	1		T65	2
valid_sources[0x03]	159	1		T38	2		T17	2		T46	1
valid_sources[0x04]	89	1		T191	2		T192	1		T64	1
valid_sources[0x05]	106	1		T133	2		T193	4		T64	2
valid_sources[0x06]	84	1		T64	2		T65	1		T86	8
valid_sources[0x07]	60	1		T48	4		T168	1		T173	1
valid_sources[0x08]	75	1		T13	1		T130	1		T64	2
valid_sources[0x09]	79	1		T27	2		T194	2		T195	1
valid_sources[0x0a]	105	1		T191	1		T161	1		T196	2
valid_sources[0x0b]	84	1		T7	1		T40	1		T156	1
valid_sources[0x0c]	102	1		T197	1		T198	3		T77	16
valid_sources[0x0d]	125	1		T199	1		T200	1		T77	16
valid_sources[0x0e]	107	1		T191	2		T133	1		T151	1
valid_sources[0x0f]	99	1		T201	1		T202	1		T64	2
valid_sources[0x10]	479	1		T194	1		T147	1		T203	1
valid_sources[0x11]	84	1		T10	2		T24	1		T204	1
valid_sources[0x12]	83	1		T1	1		T197	1		T205	2
valid_sources[0x13]	83	1		T206	2		T64	1		T65	3
valid_sources[0x14]	345	1		T10	1		T197	1		T201	1
valid_sources[0x15]	88	1		T34	1		T207	1		T200	1
valid_sources[0x16]	87	1		T41	1		T25	1		T208	3
valid_sources[0x17]	345	1		T3	2		T48	1		T136	1
valid_sources[0x18]	96	1		T197	1		T64	3		T65	5
valid_sources[0x19]	107	1		T209	1		T65	4		T77	16
valid_sources[0x1a]	100	1		T24	1		T165	1		T204	1
valid_sources[0x1b]	84	1		T32	1		T194	2		T86	2
valid_sources[0x1c]	100	1		T10	1		T64	1		T61	4
valid_sources[0x1d]	77	1		T2	1		T73	4		T166	1
valid_sources[0x1e]	141	1		T197	1		T210	1		T191	2
valid_sources[0x1f]	100	1		T34	1		T64	2		T65	3
valid_sources[0x20]	104	1		T211	1		T64	1		T65	3
valid_sources[0x21]	123	1		T212	2		T213	1		T64	1
valid_sources[0x22]	100	1		T9	2		T161	1		T202	1
valid_sources[0x23]	85	1		T13	1		T159	1		T214	1
valid_sources[0x24]	98	1		T2	1		T215	7		T204	1
valid_sources[0x25]	90	1		T65	2		T93	4		T86	2
valid_sources[0x26]	102	1		T58	1		T197	2		T216	11
valid_sources[0x27]	72	1		T27	2		T159	1		T64	1
valid_sources[0x28]	103	1		T185	1		T61	11		T77	1
valid_sources[0x29]	119	1		T206	2		T76	1		T217	1
valid_sources[0x2a]	65	1		T197	1		T142	1		T218	1
valid_sources[0x2b]	83	1		T65	1		T77	15		T86	3
valid_sources[0x2c]	99	1		T1	1		T153	1		T219	1
valid_sources[0x2d]	87	1		T1	1		T19	1		T90	1
valid_sources[0x2e]	113	1		T6	1		T196	1		T64	2
valid_sources[0x2f]	76	1		T38	1		T130	1		T198	4
valid_sources[0x30]	87	1		T140	1		T61	2		T65	2
valid_sources[0x31]	119	1		T68	6		T220	6		T202	1
valid_sources[0x32]	95	1		T221	1		T205	1		T65	1
valid_sources[0x33]	72	1		T205	2		T147	1		T65	4
valid_sources[0x34]	208	1		T222	1		T191	1		T156	1
valid_sources[0x35]	98	1		T8	1		T64	5		T86	3
valid_sources[0x36]	126	1		T223	2		T224	2		T129	2
valid_sources[0x37]	125	1		T5	1		T29	1		T164	1
valid_sources[0x38]	106	1		T225	1		T226	1		T90	2
valid_sources[0x39]	120	1		T190	1		T64	2		T62	15
valid_sources[0x3a]	132	1		T30	8		T18	4		T227	3
valid_sources[0x3b]	167	1		T25	1		T226	1		T200	3
valid_sources[0x3c]	191	1		T124	9		T76	1		T64	3
valid_sources[0x3d]	84	1		T228	2		T64	1		T86	1
valid_sources[0x3e]	238	1		T201	1		T130	1		T65	1
valid_sources[0x3f]	142	1		T50	6		T145	7		T64	3
valid_sources[0x40]	102	1		T150	1		T52	4		T202	1
valid_sources[0x41]	108	1		T17	1		T159	1		T129	2
valid_sources[0x42]	124	1		T213	1		T229	1		T64	1
valid_sources[0x43]	74	1		T64	1		T90	2		T86	4
valid_sources[0x44]	93	1		T76	1		T133	1		T203	1
valid_sources[0x45]	105	1		T64	1		T65	2		T77	21
valid_sources[0x46]	102	1		T15	1		T64	2		T67	10
valid_sources[0x47]	101	1		T225	1		T9	4		T230	4
valid_sources[0x48]	155	1		T5	1		T211	1		T64	6
valid_sources[0x49]	115	1		T159	1		T65	2		T77	21
valid_sources[0x4a]	298	1		T231	6		T232	1		T64	1
valid_sources[0x4b]	81	1		T233	1		T64	1		T65	2
valid_sources[0x4c]	117	1		T206	1		T205	1		T218	1
valid_sources[0x4d]	101	1		T34	1		T64	2		T65	1
valid_sources[0x4e]	87	1		T64	4		T65	2		T90	1
valid_sources[0x4f]	99	1		T234	1		T156	1		T141	1
valid_sources[0x50]	92	1		T235	1		T196	1		T64	3
valid_sources[0x51]	62	1		T206	1		T66	2		T64	3
valid_sources[0x52]	200	1		T64	2		T65	1		T62	23
valid_sources[0x53]	80	1		T206	1		T73	1		T236	3
valid_sources[0x54]	83	1		T201	2		T64	1		T86	2
valid_sources[0x55]	66	1		T5	1		T197	1		T64	3
valid_sources[0x56]	123	1		T5	2		T64	1		T61	10
valid_sources[0x57]	93	1		T25	1		T64	1		T65	1
valid_sources[0x58]	87	1		T148	1		T191	2		T154	1
valid_sources[0x59]	101	1		T76	2		T172	1		T146	5
valid_sources[0x5a]	64	1		T23	7		T6	1		T191	1
valid_sources[0x5b]	87	1		T142	2		T237	1		T65	1
valid_sources[0x5c]	94	1		T10	1		T6	1		T238	1
valid_sources[0x5d]	89	1		T61	11		T65	1		T87	1
valid_sources[0x5e]	105	1		T76	1		T159	1		T195	1
valid_sources[0x5f]	107	1		T206	1		T8	2		T64	1
valid_sources[0x60]	121	1		T12	1		T151	2		T65	1
valid_sources[0x61]	101	1		T2	1		T64	1		T239	14
valid_sources[0x62]	143	1		T73	1		T22	1		T159	1
valid_sources[0x63]	98	1		T136	1		T204	2		T64	1
valid_sources[0x64]	118	1		T197	1		T64	3		T65	7
valid_sources[0x65]	98	1		T25	1		T218	1		T64	4
valid_sources[0x66]	135	1		T19	1		T195	1		T64	1
valid_sources[0x67]	113	1		T141	1		T64	1		T61	2
valid_sources[0x68]	119	1		T141	1		T227	5		T65	1
valid_sources[0x69]	87	1		T240	2		T186	5		T64	1
valid_sources[0x6a]	160	1		T64	1		T61	5		T65	2
valid_sources[0x6b]	53	1		T142	1		T218	1		T241	1
valid_sources[0x6c]	64	1		T64	1		T65	1		T86	8
valid_sources[0x6d]	67	1		T162	1		T201	1		T64	2
valid_sources[0x6e]	142	1		T10	2		T33	1		T65	2
valid_sources[0x6f]	87	1		T24	2		T8	2		T9	2
valid_sources[0x70]	92	1		T21	6		T202	1		T65	3
valid_sources[0x71]	100	1		T76	1		T161	1		T232	2
valid_sources[0x72]	185	1		T204	1		T64	2		T65	1
valid_sources[0x73]	85	1		T221	1		T242	1		T195	1
valid_sources[0x74]	68	1		T64	1		T65	1		T77	12
valid_sources[0x75]	247	1		T13	1		T206	1		T64	1
valid_sources[0x76]	129	1		T38	1		T70	1		T137	6
valid_sources[0x77]	100	1		T182	1		T243	4		T163	1
valid_sources[0x78]	150	1		T24	1		T135	6		T64	4
valid_sources[0x79]	62	1		T25	1		T64	2		T86	3
valid_sources[0x7a]	83	1		T3	4		T206	1		T226	2
valid_sources[0x7b]	87	1		T156	1		T64	3		T86	6
valid_sources[0x7c]	88	1		T156	1		T64	4		T77	6
valid_sources[0x7d]	111	1		T205	1		T207	2		T142	1
valid_sources[0x7e]	81	1		T206	1		T34	1		T202	1
valid_sources[0x7f]	233	1		T1	3		T64	3		T90	1
valid_sources[0x80]	77	1		T244	5		T226	2		T65	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7363

1

T66

2

T64

82

T61

25

values[0x0]

all_enables

biggest_size

8014

1

T1

5

T4

1

T2

1

values[0x1]

all_enables

biggest_size

8013

1

T1

2

T3

2

T5

4