Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 270344 1 T1 26 T4 8 T3 10
full_word 610296 1 T1 20 T4 2 T3 6



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 880330 1 T1 46 T4 10 T3 16
auto[TlIntgErrCmd] 120 1 T61 4 T62 6 T87 8
auto[TlIntgErrData] 93 1 T61 6 T62 7 T87 5
auto[TlIntgErrBoth] 97 1 T61 10 T62 7 T87 7



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 520445 1 T1 12 T3 7 T5 7
auto[1] 360195 1 T1 34 T4 10 T3 9



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 211138 1 T1 4 T3 4 T5 4
auto[TlIntgErrNone] partial auto[1] 58923 1 T1 22 T4 8 T3 6
auto[TlIntgErrNone] full_word auto[0] 309172 1 T1 8 T3 3 T5 3
auto[TlIntgErrNone] full_word auto[1] 301097 1 T1 12 T4 2 T3 3
auto[TlIntgErrCmd] partial auto[0] 51 1 T61 3 T62 5 T87 4
auto[TlIntgErrCmd] partial auto[1] 60 1 T62 1 T87 4 T98 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T176 1 T178 1 T179 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T61 1 T177 1 T180 1
auto[TlIntgErrData] partial auto[0] 43 1 T61 2 T62 6 T87 1
auto[TlIntgErrData] partial auto[1] 40 1 T61 3 T87 3 T98 2
auto[TlIntgErrData] full_word auto[0] 2 1 T62 1 T180 1 - -
auto[TlIntgErrData] full_word auto[1] 8 1 T61 1 T87 1 T97 1
auto[TlIntgErrBoth] partial auto[0] 33 1 T61 4 T62 1 T87 2
auto[TlIntgErrBoth] partial auto[1] 56 1 T61 6 T62 5 T87 4
auto[TlIntgErrBoth] full_word auto[0] 3 1 T62 1 T87 1 T181 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T176 1 T177 1 T178 1

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