Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	270344	1		T1	26		T4	8		T3	10
full_word	610296	1		T1	20		T4	2		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	880330	1		T1	46		T4	10		T3	16
auto[TlIntgErrCmd]	120	1		T61	4		T62	6		T87	8
auto[TlIntgErrData]	93	1		T61	6		T62	7		T87	5
auto[TlIntgErrBoth]	97	1		T61	10		T62	7		T87	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	520445	1		T1	12		T3	7		T5	7
auto[1]	360195	1		T1	34		T4	10		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	211138	1		T1	4		T3	4		T5	4
auto[TlIntgErrNone]	partial	auto[1]	58923	1		T1	22		T4	8		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	309172	1		T1	8		T3	3		T5	3
auto[TlIntgErrNone]	full_word	auto[1]	301097	1		T1	12		T4	2		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	51	1		T61	3		T62	5		T87	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T62	1		T87	4		T98	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T176	1		T178	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T61	1		T177	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T61	2		T62	6		T87	1
auto[TlIntgErrData]	partial	auto[1]	40	1		T61	3		T87	3		T98	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T62	1		T180	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1		T61	1		T87	1		T97	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T61	4		T62	1		T87	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T61	6		T62	5		T87	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T62	1		T87	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T176	1		T177	1		T178	1