SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 105881328 | 16470 | 0 | 0 |
late_debug_enable_rd_A | 105881328 | 4269 | 0 | 0 |
late_debug_enable_regwen_rd_A | 105881328 | 3062 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 105881328 | 16470 | 0 | 0 |
T61 | 96554 | 7 | 0 | 0 |
T62 | 56098 | 6 | 0 | 0 |
T63 | 19035 | 68 | 0 | 0 |
T64 | 3291 | 220 | 0 | 0 |
T65 | 7511 | 282 | 0 | 0 |
T77 | 251880 | 730 | 0 | 0 |
T85 | 12674 | 387 | 0 | 0 |
T86 | 7537 | 662 | 0 | 0 |
T87 | 96475 | 7 | 0 | 0 |
T88 | 216397 | 167 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 105881328 | 4269 | 0 | 0 |
T67 | 24345 | 39 | 0 | 0 |
T77 | 251880 | 497 | 0 | 0 |
T78 | 811634 | 164 | 0 | 0 |
T89 | 20308 | 6 | 0 | 0 |
T90 | 45410 | 76 | 0 | 0 |
T91 | 232697 | 918 | 0 | 0 |
T93 | 9646 | 7 | 0 | 0 |
T96 | 15267 | 12 | 0 | 0 |
T126 | 28814 | 35 | 0 | 0 |
T127 | 11891 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 105881328 | 3062 | 0 | 0 |
T67 | 24345 | 5 | 0 | 0 |
T77 | 251880 | 419 | 0 | 0 |
T78 | 811634 | 209 | 0 | 0 |
T89 | 20308 | 8 | 0 | 0 |
T90 | 45410 | 47 | 0 | 0 |
T93 | 9646 | 2 | 0 | 0 |
T96 | 15267 | 10 | 0 | 0 |
T126 | 28814 | 36 | 0 | 0 |
T127 | 11891 | 6 | 0 | 0 |
T128 | 178093 | 30 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |