Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	39241069	4966971	0	0
MemTLResponseWithoutDebugIsError_A	39241069	0	0	0
NdmResetAckNeedsDebug_A	39241069	25	0	0
SbaTLRequestNeedsDebug_A	39241069	12549	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39241069	4966971	0	0
T1	48405	24797	0	0
T2	7173	0	0	0
T3	490085	68354	0	0
T4	187474	180420	0	0
T5	437970	108858	0	0
T7	0	11343	0	0
T10	299478	0	0	0
T11	205089	0	0	0
T13	0	27261	0	0
T15	32956	31941	0	0
T23	0	15503	0	0
T27	0	104670	0	0
T34	0	42614	0	0
T38	1833	0	0	0
T39	1112	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39241069	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39241069	25	0	0
T3	490085	1	0	0
T5	437970	1	0	0
T8	0	1	0	0
T10	299478	0	0	0
T11	205089	0	0	0
T12	16624	0	0	0
T13	130169	0	0	0
T15	32956	0	0	0
T17	0	1	0	0
T23	0	1	0	0
T27	0	1	0	0
T38	1833	0	0	0
T39	1112	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	7629	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39241069	12549	0	0
T10	299478	88	0	0
T11	205089	90	0	0
T12	16624	5	0	0
T13	130169	0	0	0
T24	0	125	0	0
T25	0	742	0	0
T26	0	364	0	0
T39	1112	0	0	0
T41	75281	60	0	0
T47	33538	0	0	0
T48	0	49	0	0
T53	7629	0	0	0
T54	100962	14	0	0
T55	0	12	0	0
T56	2878	0	0	0