Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T2 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8984908 |
8983584 |
0 |
0 |
selKnown1 |
45724018 |
45722694 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8984908 |
8983584 |
0 |
0 |
T1 |
39641 |
39637 |
0 |
0 |
T2 |
284 |
280 |
0 |
0 |
T3 |
18284 |
18280 |
0 |
0 |
T4 |
16667 |
16663 |
0 |
0 |
T5 |
27568 |
27564 |
0 |
0 |
T10 |
35392 |
35388 |
0 |
0 |
T11 |
22707 |
22703 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T15 |
20579 |
20575 |
0 |
0 |
T24 |
0 |
16 |
0 |
0 |
T25 |
0 |
20 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
T38 |
774 |
770 |
0 |
0 |
T39 |
1999 |
1995 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T48 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45724018 |
45722694 |
0 |
0 |
T1 |
68230 |
68226 |
0 |
0 |
T2 |
7316 |
7312 |
0 |
0 |
T3 |
499227 |
499223 |
0 |
0 |
T4 |
195808 |
195804 |
0 |
0 |
T5 |
451761 |
451757 |
0 |
0 |
T10 |
317183 |
317179 |
0 |
0 |
T11 |
216443 |
216439 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T15 |
43246 |
43242 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T24 |
0 |
16 |
0 |
0 |
T25 |
0 |
20 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T38 |
2221 |
2217 |
0 |
0 |
T39 |
2112 |
2108 |
0 |
0 |
T48 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T2 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2501527 |
2501305 |
0 |
0 |
selKnown1 |
39241069 |
39240847 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2501527 |
2501305 |
0 |
0 |
T1 |
19815 |
19814 |
0 |
0 |
T2 |
141 |
140 |
0 |
0 |
T3 |
9136 |
9135 |
0 |
0 |
T4 |
8332 |
8331 |
0 |
0 |
T5 |
13775 |
13774 |
0 |
0 |
T10 |
17687 |
17686 |
0 |
0 |
T11 |
11352 |
11351 |
0 |
0 |
T15 |
10288 |
10287 |
0 |
0 |
T38 |
386 |
385 |
0 |
0 |
T39 |
998 |
997 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39241069 |
39240847 |
0 |
0 |
T1 |
48405 |
48404 |
0 |
0 |
T2 |
7173 |
7172 |
0 |
0 |
T3 |
490085 |
490084 |
0 |
0 |
T4 |
187474 |
187473 |
0 |
0 |
T5 |
437970 |
437969 |
0 |
0 |
T10 |
299478 |
299477 |
0 |
0 |
T11 |
205089 |
205088 |
0 |
0 |
T15 |
32956 |
32955 |
0 |
0 |
T38 |
1833 |
1832 |
0 |
0 |
T39 |
1112 |
1111 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T2 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
594 |
372 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
9 |
8 |
0 |
0 |
T10 |
9 |
8 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T27 |
0 |
6 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
569 |
347 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T10 |
9 |
8 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T2 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6480929 |
6480489 |
0 |
0 |
selKnown1 |
6480721 |
6480281 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6480929 |
6480489 |
0 |
0 |
T1 |
19816 |
19815 |
0 |
0 |
T2 |
141 |
140 |
0 |
0 |
T3 |
9137 |
9136 |
0 |
0 |
T4 |
8333 |
8332 |
0 |
0 |
T5 |
13775 |
13774 |
0 |
0 |
T10 |
17687 |
17686 |
0 |
0 |
T11 |
11353 |
11352 |
0 |
0 |
T15 |
10289 |
10288 |
0 |
0 |
T38 |
386 |
385 |
0 |
0 |
T39 |
999 |
998 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6480721 |
6480281 |
0 |
0 |
T1 |
19815 |
19814 |
0 |
0 |
T2 |
141 |
140 |
0 |
0 |
T3 |
9136 |
9135 |
0 |
0 |
T4 |
8332 |
8331 |
0 |
0 |
T5 |
13775 |
13774 |
0 |
0 |
T10 |
17687 |
17686 |
0 |
0 |
T11 |
11352 |
11351 |
0 |
0 |
T15 |
10288 |
10287 |
0 |
0 |
T38 |
386 |
385 |
0 |
0 |
T39 |
998 |
997 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T2 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1858 |
1418 |
0 |
0 |
selKnown1 |
1659 |
1219 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1858 |
1418 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
8 |
7 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
9 |
8 |
0 |
0 |
T10 |
9 |
8 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T27 |
0 |
7 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1659 |
1219 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T10 |
9 |
8 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |