Module Definition
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Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_en_sync_copies

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_pm_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.13 86.27 72.22 57.14 75.00 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
79.81 98.04 77.78 85.71 87.50 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_en_sync_copies

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_pm_en_sync

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1332 1332 0 0
OutputsKnown_A 235446414 235219038 0 0
gen_flops.OutputDelay_A 117723207 117604398 0 1998
gen_no_flops.OutputDelay_A 117723207 117609519 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1332 1332 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0
T15 6 6 0 0
T38 6 6 0 0
T39 6 6 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 235446414 235219038 0 0
T1 290430 288438 0 0
T2 43038 42498 0 0
T3 2940510 2939262 0 0
T4 1124844 1124466 0 0
T5 2627820 2624466 0 0
T10 1796868 1793154 0 0
T11 1230534 1230144 0 0
T15 197736 197340 0 0
T38 10998 10590 0 0
T39 6672 6300 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117723207 117604398 0 1998
T1 145215 144174 0 9
T2 21519 21240 0 9
T3 1470255 1469604 0 9
T4 562422 562224 0 9
T5 1313910 1312161 0 9
T10 898434 896496 0 9
T11 615267 615063 0 9
T15 98868 98661 0 9
T38 5499 5286 0 9
T39 3336 3141 0 9

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117723207 117609519 0 0
T1 145215 144219 0 0
T2 21519 21249 0 0
T3 1470255 1469631 0 0
T4 562422 562233 0 0
T5 1313910 1312233 0 0
T10 898434 896577 0 0
T11 615267 615072 0 0
T15 98868 98670 0 0
T38 5499 5295 0 0
T39 3336 3150 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 222 222 0 0
OutputsKnown_A 39241069 39203173 0 0
gen_flops.OutputDelay_A 39241069 39201466 0 666


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222 222 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39201466 0 666
T1 48405 48058 0 3
T2 7173 7080 0 3
T3 490085 489868 0 3
T4 187474 187408 0 3
T5 437970 437387 0 3
T10 299478 298832 0 3
T11 205089 205021 0 3
T15 32956 32887 0 3
T38 1833 1762 0 3
T39 1112 1047 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 222 222 0 0
OutputsKnown_A 39241069 39203173 0 0
gen_flops.OutputDelay_A 39241069 39201466 0 666


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222 222 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39201466 0 666
T1 48405 48058 0 3
T2 7173 7080 0 3
T3 490085 489868 0 3
T4 187474 187408 0 3
T5 437970 437387 0 3
T10 299478 298832 0 3
T11 205089 205021 0 3
T15 32956 32887 0 3
T38 1833 1762 0 3
T39 1112 1047 0 3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 222 222 0 0
OutputsKnown_A 39241069 39203173 0 0
gen_no_flops.OutputDelay_A 39241069 39203173 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222 222 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

Line Coverage for Instance : tb.dut.u_pm_en_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_pm_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 222 222 0 0
OutputsKnown_A 39241069 39203173 0 0
gen_flops.OutputDelay_A 39241069 39201466 0 666


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222 222 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39201466 0 666
T1 48405 48058 0 3
T2 7173 7080 0 3
T3 490085 489868 0 3
T4 187474 187408 0 3
T5 437970 437387 0 3
T10 299478 298832 0 3
T11 205089 205021 0 3
T15 32956 32887 0 3
T38 1833 1762 0 3
T39 1112 1047 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 222 222 0 0
OutputsKnown_A 39241069 39203173 0 0
gen_no_flops.OutputDelay_A 39241069 39203173 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222 222 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 222 222 0 0
OutputsKnown_A 39241069 39203173 0 0
gen_no_flops.OutputDelay_A 39241069 39203173 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222 222 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 39241069 39203173 0 0
T1 48405 48073 0 0
T2 7173 7083 0 0
T3 490085 489877 0 0
T4 187474 187411 0 0
T5 437970 437411 0 0
T10 299478 298859 0 0
T11 205089 205024 0 0
T15 32956 32890 0 0
T38 1833 1765 0 0
T39 1112 1050 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%