SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 39241069 | 39203173 | 0 | 0 |
gen_no_flops.OutputDelay_A | 39241069 | 39203173 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 39241069 | 39203173 | 0 | 0 |
T1 | 48405 | 48073 | 0 | 0 |
T2 | 7173 | 7083 | 0 | 0 |
T3 | 490085 | 489877 | 0 | 0 |
T4 | 187474 | 187411 | 0 | 0 |
T5 | 437970 | 437411 | 0 | 0 |
T10 | 299478 | 298859 | 0 | 0 |
T11 | 205089 | 205024 | 0 | 0 |
T15 | 32956 | 32890 | 0 | 0 |
T38 | 1833 | 1765 | 0 | 0 |
T39 | 1112 | 1050 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 39241069 | 39203173 | 0 | 0 |
T1 | 48405 | 48073 | 0 | 0 |
T2 | 7173 | 7083 | 0 | 0 |
T3 | 490085 | 489877 | 0 | 0 |
T4 | 187474 | 187411 | 0 | 0 |
T5 | 437970 | 437411 | 0 | 0 |
T10 | 299478 | 298859 | 0 | 0 |
T11 | 205089 | 205024 | 0 | 0 |
T15 | 32956 | 32890 | 0 | 0 |
T38 | 1833 | 1765 | 0 | 0 |
T39 | 1112 | 1050 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |