SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
83.12 | 95.77 | 81.66 | 89.91 | 75.00 | 86.50 | 97.90 | 55.12 |
T300 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2732997754 | Jul 18 05:18:19 PM PDT 24 | Jul 18 05:19:31 PM PDT 24 | 93483304721 ps | ||
T100 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.588503042 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:47 PM PDT 24 | 236055921 ps | ||
T77 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.146521856 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:43 PM PDT 24 | 174241275 ps | ||
T125 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4211101552 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:23 PM PDT 24 | 1578566990 ps | ||
T78 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2788479904 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:18 PM PDT 24 | 1975269722 ps | ||
T301 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3603135310 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:19 PM PDT 24 | 3841457501 ps | ||
T75 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.142761299 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:34 PM PDT 24 | 56607988566 ps | ||
T302 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1120724282 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:57 PM PDT 24 | 6183802972 ps | ||
T101 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1484531181 | Jul 18 05:17:42 PM PDT 24 | Jul 18 05:17:53 PM PDT 24 | 11940970176 ps | ||
T303 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1006678788 | Jul 18 05:18:07 PM PDT 24 | Jul 18 05:18:13 PM PDT 24 | 230489977 ps | ||
T102 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4264590363 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:47 PM PDT 24 | 5771829438 ps | ||
T126 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.513416179 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:13 PM PDT 24 | 4710606385 ps | ||
T304 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1151400426 | Jul 18 05:18:20 PM PDT 24 | Jul 18 05:18:23 PM PDT 24 | 163484541 ps | ||
T106 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.39512403 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:45 PM PDT 24 | 1906273222 ps | ||
T305 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1760007197 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:26 PM PDT 24 | 17696120545 ps | ||
T306 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3574921133 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:18:06 PM PDT 24 | 72085398866 ps | ||
T307 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2722862726 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:19:25 PM PDT 24 | 27045539855 ps | ||
T97 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2928895656 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:48 PM PDT 24 | 1171159306 ps | ||
T308 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3254200167 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 144534849 ps | ||
T309 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.118846223 | Jul 18 05:17:13 PM PDT 24 | Jul 18 05:17:17 PM PDT 24 | 179385550 ps | ||
T310 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.47385610 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:44 PM PDT 24 | 420426542 ps | ||
T311 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3233786029 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:17:15 PM PDT 24 | 707040824 ps | ||
T98 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1640270087 | Jul 18 05:17:42 PM PDT 24 | Jul 18 05:17:49 PM PDT 24 | 346637357 ps | ||
T312 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1072139446 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:16 PM PDT 24 | 2894813824 ps | ||
T99 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1056194531 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:45 PM PDT 24 | 217437420 ps | ||
T313 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3176965835 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:18:08 PM PDT 24 | 20970337046 ps | ||
T107 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1188244767 | Jul 18 05:18:07 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 643510704 ps | ||
T314 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.519633703 | Jul 18 05:18:16 PM PDT 24 | Jul 18 05:18:23 PM PDT 24 | 1786534026 ps | ||
T315 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3106115857 | Jul 18 05:17:13 PM PDT 24 | Jul 18 05:17:18 PM PDT 24 | 115568624 ps | ||
T316 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1639317782 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:45 PM PDT 24 | 52815856 ps | ||
T317 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3891210585 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 1010400205 ps | ||
T318 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2636251677 | Jul 18 05:18:04 PM PDT 24 | Jul 18 05:18:07 PM PDT 24 | 3135599432 ps | ||
T115 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3522220042 | Jul 18 05:18:11 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 277351927 ps | ||
T319 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3207222092 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:15 PM PDT 24 | 330194321 ps | ||
T116 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3010318501 | Jul 18 05:18:19 PM PDT 24 | Jul 18 05:18:24 PM PDT 24 | 213156920 ps | ||
T155 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1983366694 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:21 PM PDT 24 | 1376397648 ps | ||
T320 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3973747288 | Jul 18 05:17:14 PM PDT 24 | Jul 18 05:17:33 PM PDT 24 | 5581349639 ps | ||
T157 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3501788315 | Jul 18 05:18:04 PM PDT 24 | Jul 18 05:18:19 PM PDT 24 | 2014567940 ps | ||
T321 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3787545212 | Jul 18 05:18:55 PM PDT 24 | Jul 18 05:18:57 PM PDT 24 | 152360097 ps | ||
T322 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4263271000 | Jul 18 05:18:19 PM PDT 24 | Jul 18 05:18:25 PM PDT 24 | 139050190 ps | ||
T323 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1820479685 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:17:18 PM PDT 24 | 987647840 ps | ||
T117 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2934165645 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:18:35 PM PDT 24 | 1484093398 ps | ||
T161 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2843269153 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:33 PM PDT 24 | 11491993022 ps | ||
T108 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1251532133 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:51 PM PDT 24 | 646665403 ps | ||
T324 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2288038056 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 2603895068 ps | ||
T325 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3557548545 | Jul 18 05:18:19 PM PDT 24 | Jul 18 05:18:26 PM PDT 24 | 502504398 ps | ||
T326 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3337889640 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:44 PM PDT 24 | 279314788 ps | ||
T327 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1794152238 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:15 PM PDT 24 | 255262609 ps | ||
T328 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1170195209 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:43 PM PDT 24 | 101743732 ps | ||
T329 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1180186801 | Jul 18 05:18:20 PM PDT 24 | Jul 18 05:18:24 PM PDT 24 | 286766359 ps | ||
T330 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1823727957 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:16 PM PDT 24 | 174028403 ps | ||
T331 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.698076133 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:46 PM PDT 24 | 6613644747 ps | ||
T332 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1411152424 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:45 PM PDT 24 | 432839919 ps | ||
T333 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1206353959 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:17:41 PM PDT 24 | 623275746 ps | ||
T103 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.894392178 | Jul 18 05:17:10 PM PDT 24 | Jul 18 05:17:22 PM PDT 24 | 4735013307 ps | ||
T334 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2045536110 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:45 PM PDT 24 | 135586262 ps | ||
T335 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2636723899 | Jul 18 05:17:36 PM PDT 24 | Jul 18 05:17:37 PM PDT 24 | 71787274 ps | ||
T152 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.524132401 | Jul 18 05:18:11 PM PDT 24 | Jul 18 05:18:21 PM PDT 24 | 608187297 ps | ||
T118 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2958656358 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:48 PM PDT 24 | 155947143 ps | ||
T336 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.553118581 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:44 PM PDT 24 | 624641556 ps | ||
T153 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.951920868 | Jul 18 05:18:13 PM PDT 24 | Jul 18 05:18:20 PM PDT 24 | 88764085 ps | ||
T337 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2613760435 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:18:06 PM PDT 24 | 14489773017 ps | ||
T154 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.230678390 | Jul 18 05:18:03 PM PDT 24 | Jul 18 05:18:28 PM PDT 24 | 25443107613 ps | ||
T338 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3877847779 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:42 PM PDT 24 | 518783701 ps | ||
T339 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2527229650 | Jul 18 05:18:15 PM PDT 24 | Jul 18 05:19:24 PM PDT 24 | 25403522944 ps | ||
T109 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2808524835 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:41 PM PDT 24 | 264379831 ps | ||
T340 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2298726200 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:18:12 PM PDT 24 | 9773065987 ps | ||
T160 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2764525408 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:36 PM PDT 24 | 16013659826 ps | ||
T156 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1324326903 | Jul 18 05:18:19 PM PDT 24 | Jul 18 05:18:32 PM PDT 24 | 2824993720 ps | ||
T164 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2703410058 | Jul 18 05:18:16 PM PDT 24 | Jul 18 05:18:30 PM PDT 24 | 1569216507 ps | ||
T104 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4058785451 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:47 PM PDT 24 | 6733264146 ps | ||
T341 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3075311642 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 512786577 ps | ||
T342 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4281539011 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:19:12 PM PDT 24 | 31463685150 ps | ||
T343 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1849702342 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:19:01 PM PDT 24 | 59136483327 ps | ||
T344 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2708341175 | Jul 18 05:17:10 PM PDT 24 | Jul 18 05:17:13 PM PDT 24 | 123379863 ps | ||
T345 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4140433213 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:51 PM PDT 24 | 6347385200 ps | ||
T346 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.279486016 | Jul 18 05:18:12 PM PDT 24 | Jul 18 05:18:21 PM PDT 24 | 3516371212 ps | ||
T347 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3460058749 | Jul 18 05:18:24 PM PDT 24 | Jul 18 05:18:31 PM PDT 24 | 3273978376 ps | ||
T348 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.993958725 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:14 PM PDT 24 | 312935877 ps | ||
T162 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1430322469 | Jul 18 05:18:24 PM PDT 24 | Jul 18 05:18:38 PM PDT 24 | 1836156103 ps | ||
T349 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3728466397 | Jul 18 05:18:03 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 17171567286 ps | ||
T350 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2645184867 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:44 PM PDT 24 | 75411105 ps | ||
T119 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4195635505 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:09 PM PDT 24 | 247440547 ps | ||
T351 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3496616345 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:15 PM PDT 24 | 12588587514 ps | ||
T352 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.23391768 | Jul 18 05:18:10 PM PDT 24 | Jul 18 05:18:20 PM PDT 24 | 7533478259 ps | ||
T120 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.363230525 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:18:58 PM PDT 24 | 6971391348 ps | ||
T353 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2737957341 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:14 PM PDT 24 | 183456757 ps | ||
T354 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.524429552 | Jul 18 05:18:10 PM PDT 24 | Jul 18 05:18:25 PM PDT 24 | 6154899983 ps | ||
T165 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.432695956 | Jul 18 05:18:16 PM PDT 24 | Jul 18 05:18:37 PM PDT 24 | 2389561275 ps | ||
T355 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1296635237 | Jul 18 05:18:10 PM PDT 24 | Jul 18 05:18:16 PM PDT 24 | 162698687 ps | ||
T121 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3517414173 | Jul 18 05:18:11 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 74728943 ps | ||
T356 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3103024876 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:17 PM PDT 24 | 1061670127 ps | ||
T357 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3982878849 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 405885187 ps | ||
T358 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2194433339 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:57 PM PDT 24 | 11301704444 ps | ||
T359 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1257315548 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:17:14 PM PDT 24 | 160984798 ps | ||
T360 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4264155478 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:43 PM PDT 24 | 208394913 ps | ||
T361 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3014301721 | Jul 18 05:18:25 PM PDT 24 | Jul 18 05:18:34 PM PDT 24 | 5857749309 ps | ||
T362 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3425917836 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:14 PM PDT 24 | 348971333 ps | ||
T110 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2059463835 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 263601079 ps | ||
T363 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3175363368 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:30 PM PDT 24 | 21674659633 ps | ||
T159 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4054298860 | Jul 18 05:18:04 PM PDT 24 | Jul 18 05:18:30 PM PDT 24 | 5409241977 ps | ||
T364 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2677437451 | Jul 18 05:18:07 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 245673096 ps | ||
T365 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.677620429 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:19:38 PM PDT 24 | 57759544162 ps | ||
T111 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1320004016 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:23:46 PM PDT 24 | 121266747207 ps | ||
T366 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2397394181 | Jul 18 05:18:23 PM PDT 24 | Jul 18 05:18:28 PM PDT 24 | 54592864 ps | ||
T367 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1024492767 | Jul 18 05:18:07 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 111885716 ps | ||
T368 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.129851027 | Jul 18 05:18:12 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 141050982 ps | ||
T369 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3613604672 | Jul 18 05:18:04 PM PDT 24 | Jul 18 05:18:06 PM PDT 24 | 547664011 ps | ||
T122 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2187928360 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:22 PM PDT 24 | 1204047512 ps | ||
T123 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1677744197 | Jul 18 05:18:25 PM PDT 24 | Jul 18 05:18:37 PM PDT 24 | 1727391411 ps | ||
T370 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4265222271 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:43 PM PDT 24 | 124472497 ps | ||
T371 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.579069564 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:44 PM PDT 24 | 166491530 ps | ||
T372 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.125888962 | Jul 18 05:17:43 PM PDT 24 | Jul 18 05:17:49 PM PDT 24 | 777532684 ps | ||
T124 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3628501884 | Jul 18 05:18:04 PM PDT 24 | Jul 18 05:18:13 PM PDT 24 | 2130160192 ps | ||
T373 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1005999401 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 161998517 ps | ||
T374 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1899133885 | Jul 18 05:17:37 PM PDT 24 | Jul 18 05:17:41 PM PDT 24 | 4206440286 ps | ||
T375 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4282334259 | Jul 18 05:17:09 PM PDT 24 | Jul 18 05:18:35 PM PDT 24 | 56472661718 ps | ||
T376 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.893777716 | Jul 18 05:18:07 PM PDT 24 | Jul 18 05:18:15 PM PDT 24 | 7609221290 ps | ||
T377 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.588925112 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:17:29 PM PDT 24 | 8118129446 ps | ||
T378 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3341481047 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:48 PM PDT 24 | 2983833844 ps | ||
T112 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3676618036 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 361019903 ps | ||
T158 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1756133807 | Jul 18 05:25:59 PM PDT 24 | Jul 18 05:26:11 PM PDT 24 | 2692341955 ps | ||
T379 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1512433266 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:59 PM PDT 24 | 28749730233 ps | ||
T380 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3778125934 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:47 PM PDT 24 | 294186203 ps | ||
T381 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1410970117 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 1467236012 ps | ||
T382 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4188669000 | Jul 18 05:18:17 PM PDT 24 | Jul 18 05:18:22 PM PDT 24 | 82922799 ps | ||
T383 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4019878007 | Jul 18 05:17:36 PM PDT 24 | Jul 18 05:17:37 PM PDT 24 | 76300630 ps | ||
T384 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.916150984 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:48 PM PDT 24 | 312851940 ps | ||
T385 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2868957980 | Jul 18 05:18:12 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 302695046 ps | ||
T386 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1052533135 | Jul 18 05:25:15 PM PDT 24 | Jul 18 05:26:02 PM PDT 24 | 20923533371 ps | ||
T387 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.299508840 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:09 PM PDT 24 | 151261093 ps | ||
T113 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2557443965 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:15 PM PDT 24 | 515056868 ps | ||
T388 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.106770777 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 12123141504 ps | ||
T114 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.583630729 | Jul 18 05:18:10 PM PDT 24 | Jul 18 05:18:21 PM PDT 24 | 332298398 ps | ||
T389 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1326914855 | Jul 18 05:17:13 PM PDT 24 | Jul 18 05:17:22 PM PDT 24 | 799451458 ps | ||
T390 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1186679466 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:09 PM PDT 24 | 195945640 ps | ||
T391 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.99724967 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:26 PM PDT 24 | 1741388773 ps | ||
T392 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2419691099 | Jul 18 05:18:04 PM PDT 24 | Jul 18 05:18:16 PM PDT 24 | 1420270420 ps | ||
T393 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1226349158 | Jul 18 05:17:36 PM PDT 24 | Jul 18 05:18:55 PM PDT 24 | 8922910763 ps | ||
T394 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3747675238 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:17:47 PM PDT 24 | 544263851 ps | ||
T395 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3783713720 | Jul 18 05:18:13 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 285635416 ps | ||
T163 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4195259327 | Jul 18 05:17:38 PM PDT 24 | Jul 18 05:18:01 PM PDT 24 | 2594913948 ps | ||
T396 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1298008494 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:48 PM PDT 24 | 175332091 ps | ||
T397 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.463837419 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:18:13 PM PDT 24 | 1213827922 ps | ||
T398 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1228606794 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:12 PM PDT 24 | 840449893 ps | ||
T399 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2824297148 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:46 PM PDT 24 | 90628363 ps | ||
T400 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.889309553 | Jul 18 05:18:12 PM PDT 24 | Jul 18 05:18:21 PM PDT 24 | 400355566 ps | ||
T401 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1485370096 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:36 PM PDT 24 | 6889905656 ps | ||
T402 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1091012373 | Jul 18 05:18:23 PM PDT 24 | Jul 18 05:18:37 PM PDT 24 | 756399221 ps | ||
T166 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4089933444 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:53 PM PDT 24 | 777364370 ps | ||
T403 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3034055046 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 216512891 ps | ||
T404 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2760485398 | Jul 18 05:17:09 PM PDT 24 | Jul 18 05:17:46 PM PDT 24 | 9846570479 ps | ||
T405 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.470759138 | Jul 18 05:18:17 PM PDT 24 | Jul 18 05:18:33 PM PDT 24 | 1929347404 ps | ||
T406 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3698755457 | Jul 18 05:18:54 PM PDT 24 | Jul 18 05:18:57 PM PDT 24 | 422869224 ps | ||
T407 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.234998620 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:09 PM PDT 24 | 132689128 ps | ||
T408 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.209180425 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:11 PM PDT 24 | 799460574 ps | ||
T409 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2026785933 | Jul 18 05:18:08 PM PDT 24 | Jul 18 05:18:13 PM PDT 24 | 347819928 ps | ||
T410 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1627455422 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:15 PM PDT 24 | 374766331 ps | ||
T411 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3861915274 | Jul 18 05:18:17 PM PDT 24 | Jul 18 05:18:22 PM PDT 24 | 1473596149 ps | ||
T412 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3549922494 | Jul 18 05:17:40 PM PDT 24 | Jul 18 05:17:44 PM PDT 24 | 61998329 ps | ||
T413 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2199659292 | Jul 18 05:17:37 PM PDT 24 | Jul 18 05:18:05 PM PDT 24 | 32348924049 ps | ||
T414 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2588818186 | Jul 18 05:17:11 PM PDT 24 | Jul 18 05:17:15 PM PDT 24 | 582468399 ps | ||
T415 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2861975080 | Jul 18 05:17:09 PM PDT 24 | Jul 18 05:17:13 PM PDT 24 | 756658053 ps | ||
T416 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.998698706 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:14 PM PDT 24 | 3666729107 ps | ||
T105 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2559148902 | Jul 18 05:17:37 PM PDT 24 | Jul 18 05:17:42 PM PDT 24 | 2023784384 ps | ||
T417 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.864147593 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 238461697 ps | ||
T418 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1327826207 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:09 PM PDT 24 | 67472982 ps | ||
T419 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1313089537 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:10 PM PDT 24 | 721816485 ps | ||
T420 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.367535797 | Jul 18 05:18:11 PM PDT 24 | Jul 18 05:18:18 PM PDT 24 | 369255922 ps | ||
T421 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.68693125 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:16 PM PDT 24 | 145532658 ps | ||
T422 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2017113482 | Jul 18 05:18:10 PM PDT 24 | Jul 18 05:18:17 PM PDT 24 | 1596752099 ps | ||
T423 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.527611484 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:45 PM PDT 24 | 31905891 ps | ||
T424 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1007942911 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:12 PM PDT 24 | 82829918 ps | ||
T425 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2575572576 | Jul 18 05:18:16 PM PDT 24 | Jul 18 05:18:20 PM PDT 24 | 155878607 ps | ||
T426 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.917092132 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:51 PM PDT 24 | 8117393404 ps | ||
T427 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1951392708 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:16 PM PDT 24 | 347703300 ps | ||
T428 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.434394454 | Jul 18 05:18:07 PM PDT 24 | Jul 18 05:18:11 PM PDT 24 | 171901121 ps | ||
T429 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2839021178 | Jul 18 05:18:09 PM PDT 24 | Jul 18 05:18:22 PM PDT 24 | 9407146516 ps | ||
T430 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4216392969 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:18:45 PM PDT 24 | 44092577315 ps | ||
T431 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1249309111 | Jul 18 05:18:05 PM PDT 24 | Jul 18 05:18:27 PM PDT 24 | 3874270948 ps | ||
T432 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2403248118 | Jul 18 05:17:41 PM PDT 24 | Jul 18 05:17:47 PM PDT 24 | 239815780 ps | ||
T433 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.432967289 | Jul 18 05:18:16 PM PDT 24 | Jul 18 05:18:28 PM PDT 24 | 20095227069 ps | ||
T434 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.711438617 | Jul 18 05:17:12 PM PDT 24 | Jul 18 05:17:20 PM PDT 24 | 532785084 ps | ||
T435 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3185459527 | Jul 18 05:18:03 PM PDT 24 | Jul 18 05:18:12 PM PDT 24 | 1308188988 ps | ||
T436 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2576788896 | Jul 18 05:18:12 PM PDT 24 | Jul 18 05:18:24 PM PDT 24 | 2122760527 ps | ||
T437 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4262344654 | Jul 18 05:17:42 PM PDT 24 | Jul 18 05:17:48 PM PDT 24 | 674079956 ps | ||
T438 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1086096315 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:17:43 PM PDT 24 | 312201182 ps | ||
T439 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1395874918 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:11 PM PDT 24 | 205085201 ps | ||
T440 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2290733418 | Jul 18 05:18:06 PM PDT 24 | Jul 18 05:18:25 PM PDT 24 | 20299871217 ps | ||
T441 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2960662322 | Jul 18 05:18:13 PM PDT 24 | Jul 18 05:18:21 PM PDT 24 | 1046687701 ps | ||
T51 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3219219449 | Jul 18 05:17:39 PM PDT 24 | Jul 18 05:18:01 PM PDT 24 | 63828050012 ps |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.1051459370 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 4749066587 ps |
CPU time | 4.51 seconds |
Started | Jul 18 04:47:33 PM PDT 24 |
Finished | Jul 18 04:47:39 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-14ac32fa-1f21-4b54-8aa2-d6d4d0e0695d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051459370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1051459370 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3970997435 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 27662060451 ps |
CPU time | 78 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:19:01 PM PDT 24 |
Peak memory | 221804 kb |
Host | smart-18e61380-ca07-4725-9f3c-d1381f6ebddc |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970997435 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3970997435 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3058918098 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 21661923898 ps |
CPU time | 26.3 seconds |
Started | Jul 18 04:47:11 PM PDT 24 |
Finished | Jul 18 04:47:40 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-f6cd2373-c5c6-42ff-bd65-e656b46acc63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058918098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3058918098 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3515594810 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 7571443006 ps |
CPU time | 4.36 seconds |
Started | Jul 18 04:47:48 PM PDT 24 |
Finished | Jul 18 04:47:54 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-07805a62-1eea-418b-8dfc-df86e03cd2f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515594810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3515594810 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1556217474 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2628354703 ps |
CPU time | 15.44 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:25 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-b4703ffc-fa9c-4163-a536-f60607c82ba9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556217474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1556217474 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1242593291 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 15276640645 ps |
CPU time | 17.88 seconds |
Started | Jul 18 04:47:21 PM PDT 24 |
Finished | Jul 18 04:47:40 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-cfab09a0-11b5-4d34-a3fa-0695f84ee15f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242593291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1242593291 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1914209729 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 7682052446 ps |
CPU time | 76.77 seconds |
Started | Jul 18 05:17:43 PM PDT 24 |
Finished | Jul 18 05:19:03 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-f6bd8479-8fd2-4732-9b44-f434882c8fcf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914209729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1914209729 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.4051599161 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 53277957 ps |
CPU time | 0.73 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:04 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-2ceadf06-d39b-4cb9-bbd7-aa0bf8f3d935 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051599161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4051599161 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.530946344 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 397280273 ps |
CPU time | 0.96 seconds |
Started | Jul 18 04:46:38 PM PDT 24 |
Finished | Jul 18 04:46:42 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-da32d3b0-4635-4f19-9de6-391db02add2b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530946344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.530946344 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2245434918 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 68129413 ps |
CPU time | 0.96 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:14 PM PDT 24 |
Peak memory | 215064 kb |
Host | smart-3f0df404-3668-48ef-849c-9d162f0d3f6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245434918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2245434918 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.704689741 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 7001207299 ps |
CPU time | 7.86 seconds |
Started | Jul 18 04:47:32 PM PDT 24 |
Finished | Jul 18 04:47:42 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-5f0384a4-0fc1-424f-8885-53524e17857a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704689741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.704689741 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3455241883 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 3266899266 ps |
CPU time | 3.46 seconds |
Started | Jul 18 04:46:40 PM PDT 24 |
Finished | Jul 18 04:46:47 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-720fba4e-eb89-4712-8caa-e9287b3a5eb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455241883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3455241883 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.3997600132 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 676392453 ps |
CPU time | 2.07 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:13 PM PDT 24 |
Peak memory | 229204 kb |
Host | smart-89dd0574-c777-48b9-8b00-1a12883428ec |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997600132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3997600132 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.42282107 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 90551320 ps |
CPU time | 0.98 seconds |
Started | Jul 18 04:46:41 PM PDT 24 |
Finished | Jul 18 04:46:46 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-4babe209-d068-4159-b2b3-c6749351a37e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42282107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.42282107 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4054298860 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 5409241977 ps |
CPU time | 25.43 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:30 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-335fb46d-4e71-4d38-968a-0d8455b1f8cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054298860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4054298860 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.4095468433 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 6045093924 ps |
CPU time | 6.03 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:41 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-2090273a-a94e-4978-9c34-b36cc0239961 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095468433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.4095468433 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3917616303 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 630294986 ps |
CPU time | 7.91 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:23 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-38a13cba-b5aa-463f-8a6b-81e3d2e5e0fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917616303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.3917616303 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.630212822 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 83452731 ps |
CPU time | 0.83 seconds |
Started | Jul 18 04:46:40 PM PDT 24 |
Finished | Jul 18 04:46:44 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-142a5554-bd8e-4d8c-b782-6e946e72fada |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=630212822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.630212822 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.4148471015 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 5904650587 ps |
CPU time | 6.93 seconds |
Started | Jul 18 04:47:23 PM PDT 24 |
Finished | Jul 18 04:47:31 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-ee3fff3d-3709-43dc-822f-ab865e414ff2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148471015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.4148471015 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3219219449 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 63828050012 ps |
CPU time | 19.63 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:18:01 PM PDT 24 |
Peak memory | 230100 kb |
Host | smart-cb0679a5-d12e-4e40-8b10-a0afa75462a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219219449 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3219219449 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.3050895688 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 8654643906 ps |
CPU time | 24.09 seconds |
Started | Jul 18 04:47:40 PM PDT 24 |
Finished | Jul 18 04:48:06 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-54772830-081d-43d2-8b6d-52195b7af295 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050895688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3050895688 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2047545091 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 9319911257 ps |
CPU time | 4.56 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-4930961a-ebd0-4fbe-890d-3742b68fb803 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047545091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2047545091 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.3567094373 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 2858284047 ps |
CPU time | 5.44 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-cc3ce24c-b55c-45ba-bf3d-9b3fdf8e677f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567094373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3567094373 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1021888672 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 483929966 ps |
CPU time | 0.96 seconds |
Started | Jul 18 04:46:39 PM PDT 24 |
Finished | Jul 18 04:46:44 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-03fa62b3-6efb-4f5b-9639-f77f7cbe6ecc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021888672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1021888672 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.3699689082 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 248147861 ps |
CPU time | 0.91 seconds |
Started | Jul 18 04:46:43 PM PDT 24 |
Finished | Jul 18 04:46:46 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-f7c8c914-5557-4ea1-b53f-4129fb375238 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699689082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3699689082 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.2550225067 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 8284680527 ps |
CPU time | 3.98 seconds |
Started | Jul 18 04:47:37 PM PDT 24 |
Finished | Jul 18 04:47:42 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-f6df9402-07c1-41a0-8b27-910eaa85fadf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550225067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2550225067 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4264590363 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 5771829438 ps |
CPU time | 5.12 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-96ceb275-582b-42b9-90c1-4b1c8b7e4804 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264590363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.4264590363 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1983366694 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1376397648 ps |
CPU time | 9.4 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-6511da2b-bdfa-4546-ac9f-be3a38f39e9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983366694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1 983366694 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2843269153 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 11491993022 ps |
CPU time | 20.39 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:33 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-30e3686d-7710-4ee6-b3fe-077bd2c7b0f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843269153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2843269153 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.2604392237 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 6790304246 ps |
CPU time | 11.45 seconds |
Started | Jul 18 04:47:21 PM PDT 24 |
Finished | Jul 18 04:47:35 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-3ae806ee-942f-4d89-a609-fd200e851e3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604392237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2604392237 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.361390959 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3055904307 ps |
CPU time | 2.86 seconds |
Started | Jul 18 04:47:16 PM PDT 24 |
Finished | Jul 18 04:47:20 PM PDT 24 |
Peak memory | 214500 kb |
Host | smart-ae1a8117-8939-4fbf-bc53-8e99a93d0b1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361390959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.361390959 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4130415147 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 2047012910 ps |
CPU time | 6.78 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-85c04dcc-1d47-44ed-aadd-2a2dd33b2b73 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130415147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4130415147 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2788479904 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 1975269722 ps |
CPU time | 1.72 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:18 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-aa2798ef-29a3-46b2-86d2-a8b04a49ed78 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788479904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2788479904 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.1442262661 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3943151934 ps |
CPU time | 3.04 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:31 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-84b7d408-cb2e-4f1b-8d2c-2a1a14df4c2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442262661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1442262661 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.133836142 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 88037065 ps |
CPU time | 0.89 seconds |
Started | Jul 18 04:46:41 PM PDT 24 |
Finished | Jul 18 04:46:45 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-a597c1d1-04ed-4bbc-a435-30dcb3b91030 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133836142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.133836142 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.99724967 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 1741388773 ps |
CPU time | 10.94 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:26 PM PDT 24 |
Peak memory | 221800 kb |
Host | smart-ee786ff0-a881-433e-b098-201330894105 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99724967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.99724967 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2868957980 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 302695046 ps |
CPU time | 2.31 seconds |
Started | Jul 18 05:18:12 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-502b15ae-9d4e-4be4-9b21-4c4c8f5b51f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868957980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2868957980 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2764525408 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 16013659826 ps |
CPU time | 22.12 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:36 PM PDT 24 |
Peak memory | 213784 kb |
Host | smart-4f7798b3-08eb-4cc1-a5b5-f231a0c119b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764525408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 764525408 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1984574333 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 5083439042 ps |
CPU time | 14.62 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:33 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-6dda1ca8-0b99-4a7c-b208-9a328d42d337 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984574333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1984574333 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.347957820 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 208560674 ps |
CPU time | 2.61 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-f4ba9341-ca29-4ba9-918a-680249ca8e20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347957820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.347957820 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1206353959 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 623275746 ps |
CPU time | 27.48 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:17:41 PM PDT 24 |
Peak memory | 214564 kb |
Host | smart-2bccc972-e7c0-430c-b64e-44418e86c769 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206353959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1206353959 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2760485398 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 9846570479 ps |
CPU time | 35.08 seconds |
Started | Jul 18 05:17:09 PM PDT 24 |
Finished | Jul 18 05:17:46 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-90456d2e-a8d6-475f-8b77-2199f13b1c8b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760485398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2760485398 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2861975080 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 756658053 ps |
CPU time | 2.51 seconds |
Started | Jul 18 05:17:09 PM PDT 24 |
Finished | Jul 18 05:17:13 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-221aba0b-dd30-455d-b04f-b61cb9b2fbeb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861975080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2861975080 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3106115857 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 115568624 ps |
CPU time | 2.01 seconds |
Started | Jul 18 05:17:13 PM PDT 24 |
Finished | Jul 18 05:17:18 PM PDT 24 |
Peak memory | 215160 kb |
Host | smart-d558cf9f-77d2-4a0b-910e-5807637d4047 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106115857 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3106115857 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2708341175 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 123379863 ps |
CPU time | 1.65 seconds |
Started | Jul 18 05:17:10 PM PDT 24 |
Finished | Jul 18 05:17:13 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-17185f22-78bc-4351-a126-d02dafbab926 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708341175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2708341175 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3574921133 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 72085398866 ps |
CPU time | 52.99 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:18:06 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-ddd71b5b-bf4e-4714-a106-0d184c629dfd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574921133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3574921133 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.588925112 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 8118129446 ps |
CPU time | 15.67 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:17:29 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-d8556da9-f1a2-472c-8590-1a66fff94347 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588925112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r v_dm_jtag_dmi_csr_bit_bash.588925112 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.894392178 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 4735013307 ps |
CPU time | 9.57 seconds |
Started | Jul 18 05:17:10 PM PDT 24 |
Finished | Jul 18 05:17:22 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-f512a760-8ffb-4239-a9f3-627cf1237ab6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894392178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _hw_reset.894392178 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3103024876 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 1061670127 ps |
CPU time | 1.58 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:17 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-ae22c3fc-3d30-41cf-81dd-5bb0e8ebeca1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103024876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 103024876 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1485370096 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 6889905656 ps |
CPU time | 20.49 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:36 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-9465e6ee-1132-407c-88d3-86e9bb96f48c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485370096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1485370096 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1951392708 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 347703300 ps |
CPU time | 0.88 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:16 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-af7ba030-ee7c-4990-8bae-8d963e941bde |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951392708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.1951392708 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1257315548 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 160984798 ps |
CPU time | 1.02 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:17:14 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-b7511e57-d773-4968-a882-4ed9a118617a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257315548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 257315548 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.68693125 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 145532658 ps |
CPU time | 0.77 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:16 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-09b1330c-5a0f-4613-9f22-1ea6167fad03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68693125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_parti al_access.68693125 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.118846223 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 179385550 ps |
CPU time | 0.75 seconds |
Started | Jul 18 05:17:13 PM PDT 24 |
Finished | Jul 18 05:17:17 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-8d2e9947-086a-40bf-8d2e-f03ebf3bc0b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118846223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.118846223 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.711438617 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 532785084 ps |
CPU time | 4.17 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:20 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-5609db26-1d2e-4bc2-9282-8b1d28e2952b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711438617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.711438617 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4282334259 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 56472661718 ps |
CPU time | 85.3 seconds |
Started | Jul 18 05:17:09 PM PDT 24 |
Finished | Jul 18 05:18:35 PM PDT 24 |
Peak memory | 223972 kb |
Host | smart-a8a56ef7-ba51-4e7c-8db5-46d9e26c9fd8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282334259 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.4282334259 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1326914855 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 799451458 ps |
CPU time | 5.5 seconds |
Started | Jul 18 05:17:13 PM PDT 24 |
Finished | Jul 18 05:17:22 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-61a69954-e1fe-4177-8a4d-5660c798efb7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326914855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1326914855 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.39512403 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 1906273222 ps |
CPU time | 30.72 seconds |
Started | Jul 18 05:17:12 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 214616 kb |
Host | smart-ae89e11c-3947-4ed6-859d-72e69d551541 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39512403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.rv_dm_csr_aliasing.39512403 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2808524835 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 264379831 ps |
CPU time | 1.76 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:41 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-1de7eb04-62ab-4788-a3d7-64c6cde1b605 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808524835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2808524835 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.588503042 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 236055921 ps |
CPU time | 2.58 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 217044 kb |
Host | smart-9ec132c5-555f-4ebf-9a6d-e16265b27076 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588503042 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.588503042 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4261716937 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 434609220 ps |
CPU time | 2.36 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-20ab9dfb-765e-4f74-9e9f-ec0aa7b250b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261716937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4261716937 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3157050620 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 41494827650 ps |
CPU time | 115.41 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:19:36 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-4c408803-9817-4290-bbc6-c3174b41fa1c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157050620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.3157050620 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2298726200 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 9773065987 ps |
CPU time | 30.06 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:18:12 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-5f6f52ff-8c2e-4ee0-a8ca-2b79ebb92fd1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298726200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2298726200 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1484531181 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 11940970176 ps |
CPU time | 7.77 seconds |
Started | Jul 18 05:17:42 PM PDT 24 |
Finished | Jul 18 05:17:53 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-010c4097-e2e9-4ad6-b6e5-74b12e38051b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484531181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.1484531181 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1120724282 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 6183802972 ps |
CPU time | 15.84 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:57 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-e1327d9e-36ec-4185-8663-801e22c5b2a4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120724282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 120724282 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2588818186 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 582468399 ps |
CPU time | 1.1 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:17:15 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-fd95e035-bdfa-4d07-a1e3-cc0986088d26 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588818186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.2588818186 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3973747288 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 5581349639 ps |
CPU time | 16.41 seconds |
Started | Jul 18 05:17:14 PM PDT 24 |
Finished | Jul 18 05:17:33 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-93623515-fa2a-4d8d-84e1-f16568725464 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973747288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.3973747288 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1820479685 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 987647840 ps |
CPU time | 3.37 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:17:18 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-a58596d4-be47-4e2e-b864-93fe9226e7db |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820479685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1820479685 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3233786029 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 707040824 ps |
CPU time | 1.21 seconds |
Started | Jul 18 05:17:11 PM PDT 24 |
Finished | Jul 18 05:17:15 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-002b9e85-2a93-47b2-ba64-2f48d8ed2f2c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233786029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 233786029 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1639317782 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 52815856 ps |
CPU time | 0.78 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-70ff70c4-d7ac-4ee4-a782-b0f63daf9336 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639317782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1639317782 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2045536110 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 135586262 ps |
CPU time | 0.77 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-43f87b1d-fabb-4bfb-b6ac-51ced7787678 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045536110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2045536110 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2928895656 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1171159306 ps |
CPU time | 4.18 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-f549ab89-92fc-46ef-9574-4b52b320b6ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928895656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2928895656 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4195259327 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 2594913948 ps |
CPU time | 22.15 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:18:01 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-8b5ab172-b001-4698-9ecb-b5138726f193 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195259327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4195259327 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1180186801 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 286766359 ps |
CPU time | 2.27 seconds |
Started | Jul 18 05:18:20 PM PDT 24 |
Finished | Jul 18 05:18:24 PM PDT 24 |
Peak memory | 215236 kb |
Host | smart-777a5eba-83a7-412d-815e-32ce68846cf7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180186801 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1180186801 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1296635237 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 162698687 ps |
CPU time | 1.46 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:16 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-390fe314-f5a9-4c14-bfec-eb996213d150 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296635237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1296635237 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.677620429 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 57759544162 ps |
CPU time | 84.91 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:19:38 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-a8cd3b43-2a0f-4553-bcc9-11244b5e4ad8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677620429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rv_dm_jtag_dmi_csr_bit_bash.677620429 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1072139446 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 2894813824 ps |
CPU time | 3.42 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:16 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-323f3505-fe07-49f8-9776-7c85435e847b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072139446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1072139446 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3891210585 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 1010400205 ps |
CPU time | 3.35 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-1c457233-f8b1-40d4-b6fe-66e3a624e738 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891210585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 3891210585 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.367535797 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 369255922 ps |
CPU time | 2.66 seconds |
Started | Jul 18 05:18:11 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-35e22a42-fc0a-46c4-a16f-95314b33755c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367535797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.367535797 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2703410058 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1569216507 ps |
CPU time | 11.17 seconds |
Started | Jul 18 05:18:16 PM PDT 24 |
Finished | Jul 18 05:18:30 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-2e84bb6e-9b8c-4a6e-a518-f96b3951adb4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703410058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 703410058 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.889309553 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 400355566 ps |
CPU time | 4.35 seconds |
Started | Jul 18 05:18:12 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-ab6a8662-1b3f-4b6e-ba8a-22d808b260f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889309553 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.889309553 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4188669000 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 82922799 ps |
CPU time | 1.6 seconds |
Started | Jul 18 05:18:17 PM PDT 24 |
Finished | Jul 18 05:18:22 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-0786c7c7-d2f9-4db0-a1d0-8fcb3eed1aa6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188669000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4188669000 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2732997754 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 93483304721 ps |
CPU time | 69.25 seconds |
Started | Jul 18 05:18:19 PM PDT 24 |
Finished | Jul 18 05:19:31 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-bcfdf2dc-3b3c-4e89-b1cb-afd90b6e6349 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732997754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.2732997754 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.519633703 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 1786534026 ps |
CPU time | 3.37 seconds |
Started | Jul 18 05:18:16 PM PDT 24 |
Finished | Jul 18 05:18:23 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-ef3b110f-515f-4db7-afeb-f36ad3b99366 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519633703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.519633703 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3613604672 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 547664011 ps |
CPU time | 1.13 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:06 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-0fdb488f-5859-4c61-9625-14411b93f820 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613604672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3613604672 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2576788896 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 2122760527 ps |
CPU time | 7.97 seconds |
Started | Jul 18 05:18:12 PM PDT 24 |
Finished | Jul 18 05:18:24 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-b7ddd604-2c5e-4913-b049-bc5d1ce9a255 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576788896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.2576788896 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.432695956 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 2389561275 ps |
CPU time | 17.8 seconds |
Started | Jul 18 05:18:16 PM PDT 24 |
Finished | Jul 18 05:18:37 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-d65a0e08-1ea6-4ec0-8826-925b2c67a55c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432695956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.432695956 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.134137184 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 141564919 ps |
CPU time | 2.61 seconds |
Started | Jul 18 05:18:27 PM PDT 24 |
Finished | Jul 18 05:18:33 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-05fdea0f-b8a5-44e5-98d8-8beb0b4e0f3b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134137184 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.134137184 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2397394181 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 54592864 ps |
CPU time | 1.5 seconds |
Started | Jul 18 05:18:23 PM PDT 24 |
Finished | Jul 18 05:18:28 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-e42f6ff1-2b19-48dd-97d3-fd14e3a490b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397394181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2397394181 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.493411063 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 53326067310 ps |
CPU time | 33.02 seconds |
Started | Jul 18 05:18:12 PM PDT 24 |
Finished | Jul 18 05:18:49 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-0a0eb2d3-3481-4cec-aac6-2dfc3a4d548c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493411063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rv_dm_jtag_dmi_csr_bit_bash.493411063 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3460058749 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 3273978376 ps |
CPU time | 3.36 seconds |
Started | Jul 18 05:18:24 PM PDT 24 |
Finished | Jul 18 05:18:31 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-632c247c-e069-4978-beea-859d221a9fa4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460058749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3460058749 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.129851027 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 141050982 ps |
CPU time | 0.87 seconds |
Started | Jul 18 05:18:12 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-f62d0160-e4b4-4ef7-8854-154f453561af |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129851027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.129851027 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1677744197 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1727391411 ps |
CPU time | 7.92 seconds |
Started | Jul 18 05:18:25 PM PDT 24 |
Finished | Jul 18 05:18:37 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-cbbd93da-f1b4-4710-a038-c21939647aab |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677744197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1677744197 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.951920868 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 88764085 ps |
CPU time | 3.11 seconds |
Started | Jul 18 05:18:13 PM PDT 24 |
Finished | Jul 18 05:18:20 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-1eca3d94-74e5-49d3-bf9c-e3dee8fb7c67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951920868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.951920868 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1091012373 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 756399221 ps |
CPU time | 10.07 seconds |
Started | Jul 18 05:18:23 PM PDT 24 |
Finished | Jul 18 05:18:37 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-90a5a573-57dd-493a-918f-f7bd395f0987 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091012373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 091012373 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1005999401 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 161998517 ps |
CPU time | 2.5 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-f59d7540-dc9d-422e-855c-d46d39c5ddc3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005999401 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1005999401 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3010318501 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 213156920 ps |
CPU time | 2.33 seconds |
Started | Jul 18 05:18:19 PM PDT 24 |
Finished | Jul 18 05:18:24 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-fe056634-5039-4615-8529-d05fbd658102 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010318501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3010318501 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2527229650 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 25403522944 ps |
CPU time | 65.33 seconds |
Started | Jul 18 05:18:15 PM PDT 24 |
Finished | Jul 18 05:19:24 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-2854969f-9c63-4aa8-8bed-b6bdcd0e81b4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527229650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.2527229650 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3014301721 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 5857749309 ps |
CPU time | 5.4 seconds |
Started | Jul 18 05:18:25 PM PDT 24 |
Finished | Jul 18 05:18:34 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-02b9ab23-0e8e-4db3-9b59-9037c2ed4ac0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014301721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 3014301721 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2870840859 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 102344245 ps |
CPU time | 0.79 seconds |
Started | Jul 18 05:18:25 PM PDT 24 |
Finished | Jul 18 05:18:30 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-d62be930-09e5-4668-b9aa-af65b77e6463 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870840859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2870840859 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1228606794 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 840449893 ps |
CPU time | 4.17 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:12 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-5e321783-1b1d-475b-aae5-ffe07922d767 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228606794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.1228606794 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2570293520 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1373220838 ps |
CPU time | 3.23 seconds |
Started | Jul 18 05:18:14 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-bf83efa9-9714-40b2-9c72-0e60aac806c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570293520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2570293520 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1430322469 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1836156103 ps |
CPU time | 11.42 seconds |
Started | Jul 18 05:18:24 PM PDT 24 |
Finished | Jul 18 05:18:38 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-23036240-1368-406a-b1c1-e1c92a75524b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430322469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 430322469 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.998698706 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 3666729107 ps |
CPU time | 5.6 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:14 PM PDT 24 |
Peak memory | 219912 kb |
Host | smart-0f4e81f7-1213-4444-b7c1-1d2cd7a62330 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998698706 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.998698706 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4195635505 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 247440547 ps |
CPU time | 1.6 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:09 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-87a03a8c-e79d-4fb4-954a-742c0d949e4f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195635505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4195635505 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3603135310 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 3841457501 ps |
CPU time | 11.44 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:19 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-5bab8bb4-7208-46e3-8b65-1018f0e8b70f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603135310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.3603135310 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.893777716 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 7609221290 ps |
CPU time | 4.23 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-5d79e077-50ad-49e2-be71-5f38e95cf6a7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893777716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.893777716 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2677437451 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 245673096 ps |
CPU time | 0.76 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-e713fe81-d648-4545-adb3-11a6e89f3108 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677437451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 2677437451 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2187928360 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1204047512 ps |
CPU time | 7.97 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:22 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-bfaa5188-fad5-4b22-935f-751c2f46facc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187928360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.2187928360 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.524132401 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 608187297 ps |
CPU time | 5.81 seconds |
Started | Jul 18 05:18:11 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-9b84765e-eb9e-48a5-a773-d0a13a132e92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524132401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.524132401 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1249309111 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 3874270948 ps |
CPU time | 20.09 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:27 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-0332f5e4-9557-4a1f-9726-fbb8ad3de485 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249309111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 249309111 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.256711546 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 496843037 ps |
CPU time | 2.42 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-99796340-d37c-4cf7-b0bb-8b4f393d9a1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256711546 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.256711546 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.993958725 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 312935877 ps |
CPU time | 1.58 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:14 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-dd9ef8d3-60f8-489e-b866-1ae29cad17f2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993958725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.993958725 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2722862726 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 27045539855 ps |
CPU time | 71.67 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:19:25 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-19000f68-fd3a-41bd-9c92-48afb4bb1f3e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722862726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.2722862726 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.524429552 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 6154899983 ps |
CPU time | 10.79 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:25 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-5593f4a5-3c7c-446d-9e0f-ccc5128225ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524429552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.524429552 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3698755457 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 422869224 ps |
CPU time | 1.79 seconds |
Started | Jul 18 05:18:54 PM PDT 24 |
Finished | Jul 18 05:18:57 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-c9bfe885-ca5b-498d-8732-40f8df08edca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698755457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3698755457 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.583630729 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 332298398 ps |
CPU time | 6.73 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-fb5e5490-d156-4189-9324-1573595592d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583630729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.583630729 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3982878849 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 405885187 ps |
CPU time | 3.28 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-d89aaca5-6373-43e9-93cf-7a3fb839096e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982878849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3982878849 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3557548545 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 502504398 ps |
CPU time | 3.98 seconds |
Started | Jul 18 05:18:19 PM PDT 24 |
Finished | Jul 18 05:18:26 PM PDT 24 |
Peak memory | 221536 kb |
Host | smart-a30f1d1a-cd07-442a-b58e-2c4bdb1144f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557548545 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3557548545 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3522220042 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 277351927 ps |
CPU time | 1.82 seconds |
Started | Jul 18 05:18:11 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-2047e268-c7f9-4548-b48c-287d2cd9f132 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522220042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3522220042 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.23391768 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 7533478259 ps |
CPU time | 5.5 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:20 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-b59666a3-f42a-44fc-a121-9f14510ab00b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r v_dm_jtag_dmi_csr_bit_bash.23391768 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1163134072 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 13055161745 ps |
CPU time | 34.84 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:48 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-7d8b1238-4b55-458b-939e-c7f7149f49e4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163134072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 1163134072 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1794152238 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 255262609 ps |
CPU time | 0.9 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-35efeafe-7d08-4616-bb1f-0dde59dfe946 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794152238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 1794152238 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3185459527 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 1308188988 ps |
CPU time | 7.4 seconds |
Started | Jul 18 05:18:03 PM PDT 24 |
Finished | Jul 18 05:18:12 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-32e55dd4-9048-4978-a829-ebeb8de7a409 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185459527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.3185459527 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4263271000 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 139050190 ps |
CPU time | 2.99 seconds |
Started | Jul 18 05:18:19 PM PDT 24 |
Finished | Jul 18 05:18:25 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-afc8f79f-c4d2-4732-9d51-cf5f12504829 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263271000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.4263271000 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1324326903 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2824993720 ps |
CPU time | 9.89 seconds |
Started | Jul 18 05:18:19 PM PDT 24 |
Finished | Jul 18 05:18:32 PM PDT 24 |
Peak memory | 213496 kb |
Host | smart-478f5a56-f7d7-4204-9419-af9c5bf20457 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324326903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 324326903 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.279486016 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 3516371212 ps |
CPU time | 4.42 seconds |
Started | Jul 18 05:18:12 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 219148 kb |
Host | smart-b2bce893-5f81-4b93-b0a9-10dd98f3c5e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279486016 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.279486016 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3517414173 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 74728943 ps |
CPU time | 1.68 seconds |
Started | Jul 18 05:18:11 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-14daf6e6-065f-416f-adc9-535f5228b3b7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517414173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3517414173 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.432967289 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 20095227069 ps |
CPU time | 8.57 seconds |
Started | Jul 18 05:18:16 PM PDT 24 |
Finished | Jul 18 05:18:28 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-9806491f-3f7b-46e4-9a24-75f2418445ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432967289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rv_dm_jtag_dmi_csr_bit_bash.432967289 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3861915274 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1473596149 ps |
CPU time | 1.97 seconds |
Started | Jul 18 05:18:17 PM PDT 24 |
Finished | Jul 18 05:18:22 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-1af17b83-6b08-4e7f-bc33-0912551905b7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861915274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3861915274 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1151400426 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 163484541 ps |
CPU time | 0.81 seconds |
Started | Jul 18 05:18:20 PM PDT 24 |
Finished | Jul 18 05:18:23 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-eb5d58f5-a5e0-462a-b58f-bcadb61f6b4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151400426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1151400426 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2960662322 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 1046687701 ps |
CPU time | 4.65 seconds |
Started | Jul 18 05:18:13 PM PDT 24 |
Finished | Jul 18 05:18:21 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-53c015b0-9248-4e52-aab1-72a2ddfd2415 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960662322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2960662322 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3254200167 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 144534849 ps |
CPU time | 3.44 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-a338ae88-0837-46ad-9b9a-ca541f4e8d1e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254200167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3254200167 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.470759138 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1929347404 ps |
CPU time | 13.1 seconds |
Started | Jul 18 05:18:17 PM PDT 24 |
Finished | Jul 18 05:18:33 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-dc36bfb7-bdbc-4a59-8357-1d787eaf74ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470759138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.470759138 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1823727957 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 174028403 ps |
CPU time | 4.01 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:16 PM PDT 24 |
Peak memory | 221708 kb |
Host | smart-81da2d1d-329c-4950-94e9-0c5ab9b6b052 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823727957 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1823727957 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2026785933 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 347819928 ps |
CPU time | 1.43 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:13 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-345c2e13-ead2-43ac-8615-9671ffc2ab2c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026785933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2026785933 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1804238153 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2335638199 ps |
CPU time | 3.05 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:11 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-abf1bfc9-7d85-44ac-ac5e-10a79000a4ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804238153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1804238153 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3822713538 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 13747638826 ps |
CPU time | 33.9 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:39 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-c9df923a-a7d0-4e6d-b6a0-35021f2491f0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822713538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3822713538 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3783713720 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 285635416 ps |
CPU time | 0.9 seconds |
Started | Jul 18 05:18:13 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-f19dfd11-3159-4488-968f-d0cdd6f0dd69 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783713720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 3783713720 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3628501884 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 2130160192 ps |
CPU time | 7.57 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:13 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-80da7b2d-8f06-4812-855c-a77a2842729a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628501884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3628501884 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.864147593 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 238461697 ps |
CPU time | 4.65 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 213700 kb |
Host | smart-c14f9e13-5caa-47ed-acb1-a07822ce002a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864147593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.864147593 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1327826207 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 67472982 ps |
CPU time | 3.11 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:09 PM PDT 24 |
Peak memory | 221744 kb |
Host | smart-2c3c0b9e-82f3-4760-a61a-a848423c5731 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327826207 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1327826207 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1627455422 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 374766331 ps |
CPU time | 1.81 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-f6e3541f-08b1-4a96-82f4-4e5b95d0a958 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627455422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1627455422 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.106770777 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 12123141504 ps |
CPU time | 9.44 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-65abe059-cc38-4cb5-95c4-4b435957d81c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106770777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rv_dm_jtag_dmi_csr_bit_bash.106770777 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2839021178 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 9407146516 ps |
CPU time | 8.27 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:22 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-faba6275-4e15-4fec-be11-f0a9c058c03f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839021178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2839021178 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2575572576 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 155878607 ps |
CPU time | 0.77 seconds |
Started | Jul 18 05:18:16 PM PDT 24 |
Finished | Jul 18 05:18:20 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-7b027e6e-4f80-4add-8e61-e3d385f791cf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575572576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2575572576 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3676618036 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 361019903 ps |
CPU time | 4.24 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-4c6bb2d6-a289-4610-9725-70b0c9acc331 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676618036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.3676618036 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1466940334 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 503241266 ps |
CPU time | 3.41 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:16 PM PDT 24 |
Peak memory | 213788 kb |
Host | smart-23b4f961-ad54-4411-861b-72c7cabc935d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466940334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1466940334 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4211101552 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1578566990 ps |
CPU time | 10.52 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:23 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-94047042-d174-474a-9a6b-b3693b38f35a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211101552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4 211101552 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.463837419 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 1213827922 ps |
CPU time | 28.52 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:18:13 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-3921acd6-3743-420f-9719-916c6818afae |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463837419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.rv_dm_csr_aliasing.463837419 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1410970117 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1467236012 ps |
CPU time | 27.24 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-36aff705-0580-40c7-90ff-b2f5ee26f07a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410970117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1410970117 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2958656358 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 155947143 ps |
CPU time | 2.61 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-1d4fd69b-30d3-495f-8252-bddcf5bdad4f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958656358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2958656358 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.916150984 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 312851940 ps |
CPU time | 4.14 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 219860 kb |
Host | smart-437012a2-2aaf-4fb4-ad07-71403201e8a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916150984 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.916150984 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2645184867 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 75411105 ps |
CPU time | 1.65 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:44 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-8f6a2294-7fc4-4b7f-b789-5b762c1bfc98 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645184867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2645184867 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4216392969 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 44092577315 ps |
CPU time | 62.95 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:18:45 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-f3cc40f5-ba05-4ae7-b7e3-eca4f57abb58 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216392969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.4216392969 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2194433339 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 11301704444 ps |
CPU time | 12.69 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:57 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-a086d240-6c45-47e8-9489-6826bea64922 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194433339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.2194433339 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4058785451 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 6733264146 ps |
CPU time | 8.6 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-77c9f115-b2de-4fcd-a32c-e170c2fc03df |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058785451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.4058785451 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3341481047 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 2983833844 ps |
CPU time | 3.31 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-2cc29ff8-5583-499d-bd3b-7397dfd3a9aa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341481047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3 341481047 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.47385610 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 420426542 ps |
CPU time | 0.91 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:44 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-ee615b01-d120-4562-b1d5-916582db6f62 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47385610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_ aliasing.47385610 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.698076133 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 6613644747 ps |
CPU time | 6.67 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:46 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-128d1e38-ea16-4e34-826a-6de6a7a5118a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698076133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _bit_bash.698076133 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3787545212 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 152360097 ps |
CPU time | 0.81 seconds |
Started | Jul 18 05:18:55 PM PDT 24 |
Finished | Jul 18 05:18:57 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-9d6f5a0e-a4b5-4dbc-a071-2506a9ca9682 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787545212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3787545212 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.553118581 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 624641556 ps |
CPU time | 1.51 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:44 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-f7ed22a7-f4f9-487c-b35a-38bc287858ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553118581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.553118581 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.527611484 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 31905891 ps |
CPU time | 0.75 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-8dd29012-f669-43dd-8e25-331dafbd3b06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527611484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part ial_access.527611484 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4265222271 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 124472497 ps |
CPU time | 1 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:43 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-f9565df9-a8c6-4896-a63f-c14952f7b22b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265222271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4265222271 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1251532133 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 646665403 ps |
CPU time | 6.55 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:51 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-3349c5f4-5563-45a7-b0ef-3715260daa60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251532133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1251532133 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1512433266 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 28749730233 ps |
CPU time | 18.19 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:59 PM PDT 24 |
Peak memory | 221876 kb |
Host | smart-add1b451-dee5-43d6-baa6-f952571d364c |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512433266 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1512433266 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3337889640 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 279314788 ps |
CPU time | 4.74 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:44 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-d1400359-a8b1-4b46-b364-954e87220958 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337889640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3337889640 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4089933444 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 777364370 ps |
CPU time | 10.36 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:53 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-5b0e4699-92b7-40d1-8c59-d08925da5f6b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089933444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4089933444 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.363230525 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 6971391348 ps |
CPU time | 74.14 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:18:58 PM PDT 24 |
Peak memory | 218848 kb |
Host | smart-1b4991a7-a771-4161-8c3a-e476bc9f03ad |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363230525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.rv_dm_csr_aliasing.363230525 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2934165645 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1484093398 ps |
CPU time | 55.94 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:18:35 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-09dbd9d0-4b5c-4468-acc1-7f77437ee70d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934165645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2934165645 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3163686717 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 163596378 ps |
CPU time | 1.72 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:40 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-8a85e9d6-9661-43de-8b97-4538ab398f5c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163686717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3163686717 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1086096315 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 312201182 ps |
CPU time | 2.51 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:43 PM PDT 24 |
Peak memory | 221868 kb |
Host | smart-700f276f-d373-4bef-bbae-a755607611da |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086096315 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1086096315 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1056194531 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 217437420 ps |
CPU time | 1.59 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-209e1779-7942-4c9e-8fb7-bcc4a7603343 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056194531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1056194531 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2199659292 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 32348924049 ps |
CPU time | 27.67 seconds |
Started | Jul 18 05:17:37 PM PDT 24 |
Finished | Jul 18 05:18:05 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-60c8e38a-f19a-407a-b3d0-dd7a6048100e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199659292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.2199659292 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4140433213 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 6347385200 ps |
CPU time | 7.97 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:51 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-b279c689-d57b-425e-9dc2-3529cd9908b8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140433213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.4140433213 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2559148902 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 2023784384 ps |
CPU time | 4.13 seconds |
Started | Jul 18 05:17:37 PM PDT 24 |
Finished | Jul 18 05:17:42 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-5ae846cc-d2cf-4a4d-9437-512f9d96f889 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559148902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2559148902 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2613760435 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 14489773017 ps |
CPU time | 26.03 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:18:06 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-0fe99abf-b6ac-4d52-97ac-6579fc363cf1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613760435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2 613760435 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3778125934 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 294186203 ps |
CPU time | 1.1 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-47f8cc5d-5896-42ab-8a53-684147f0fd1c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778125934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3778125934 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1899133885 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 4206440286 ps |
CPU time | 2.85 seconds |
Started | Jul 18 05:17:37 PM PDT 24 |
Finished | Jul 18 05:17:41 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-80b3f099-0b3e-469c-a20c-16ecc42b3856 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899133885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1899133885 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3877847779 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 518783701 ps |
CPU time | 1.51 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:42 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-a34863af-5c7d-4899-8087-b1ffe20b257f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877847779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3877847779 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2824297148 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 90628363 ps |
CPU time | 0.81 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:46 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-049e07e6-18cd-4aa7-a5b8-a2bd473b3347 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824297148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 824297148 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4019878007 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 76300630 ps |
CPU time | 0.71 seconds |
Started | Jul 18 05:17:36 PM PDT 24 |
Finished | Jul 18 05:17:37 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-2c29752d-2685-4ab8-a4ad-bc233a2d7cd0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019878007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.4019878007 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.579069564 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 166491530 ps |
CPU time | 1.07 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:44 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-245ec8f2-86de-4d7e-9266-70c714d4c49a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579069564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.579069564 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3747675238 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 544263851 ps |
CPU time | 7.63 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-4fbec817-152c-4b81-866d-8ea76bbd4fd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747675238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.3747675238 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4264155478 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 208394913 ps |
CPU time | 3.61 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:43 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-cb6c25c9-e683-4f01-ab12-f42f79b925f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264155478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4264155478 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.554121207 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 3033326776 ps |
CPU time | 17.46 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:18:00 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-a0710c8c-2cad-42c5-805d-31824af67631 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554121207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.554121207 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1226349158 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 8922910763 ps |
CPU time | 78.12 seconds |
Started | Jul 18 05:17:36 PM PDT 24 |
Finished | Jul 18 05:18:55 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-f9316aa9-cce7-4fc0-ab07-30562215784b |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226349158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1226349158 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2288038056 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2603895068 ps |
CPU time | 34.12 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-960f4a69-230e-4965-9614-c0eb99ba8468 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288038056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2288038056 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1640270087 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 346637357 ps |
CPU time | 3.13 seconds |
Started | Jul 18 05:17:42 PM PDT 24 |
Finished | Jul 18 05:17:49 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-7c742484-e954-4f3e-abc0-d63c6951b29f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640270087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1640270087 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.917092132 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 8117393404 ps |
CPU time | 6.51 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:51 PM PDT 24 |
Peak memory | 221144 kb |
Host | smart-ab088ef9-5ef3-4b76-844b-90531478bd9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917092132 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.917092132 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3815742018 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 81022456 ps |
CPU time | 1.47 seconds |
Started | Jul 18 05:17:42 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-de101399-7c3a-4ca4-bd61-5d93b3221e14 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815742018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3815742018 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3739259413 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 23513620257 ps |
CPU time | 25.81 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:18:05 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-b499ec19-45d5-47af-b412-63a284b0b673 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739259413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3739259413 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3549922494 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 61998329 ps |
CPU time | 0.8 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:44 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-20f63213-10dc-4b81-82b6-974758b67eb8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549922494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.3549922494 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2126934707 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 7785856238 ps |
CPU time | 2.66 seconds |
Started | Jul 18 05:17:38 PM PDT 24 |
Finished | Jul 18 05:17:43 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-86aa2c6d-3b52-4f55-93da-2e9ea8c2c1b2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126934707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2 126934707 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.125888962 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 777532684 ps |
CPU time | 2.92 seconds |
Started | Jul 18 05:17:43 PM PDT 24 |
Finished | Jul 18 05:17:49 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-97c42108-4e1a-4f93-be9b-e6b8f3707dbe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125888962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.125888962 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3176965835 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 20970337046 ps |
CPU time | 22.51 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:18:08 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-576cc339-9dc1-49df-9427-6ba536ecc40f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176965835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.3176965835 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4262344654 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 674079956 ps |
CPU time | 2.46 seconds |
Started | Jul 18 05:17:42 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-a2ac202b-70a7-44f5-9b29-b17f246f32b1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262344654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.4262344654 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.146521856 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 174241275 ps |
CPU time | 0.79 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:43 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-2380f65c-19b2-4760-a593-42766ece3d40 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146521856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.146521856 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1170195209 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 101743732 ps |
CPU time | 0.74 seconds |
Started | Jul 18 05:17:39 PM PDT 24 |
Finished | Jul 18 05:17:43 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-7d1ad5da-ce6a-43e4-88de-baa6f30bacdf |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170195209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1170195209 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2636723899 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 71787274 ps |
CPU time | 0.67 seconds |
Started | Jul 18 05:17:36 PM PDT 24 |
Finished | Jul 18 05:17:37 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-c662baea-98b0-4c53-823b-3f860deba640 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636723899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2636723899 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1298008494 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 175332091 ps |
CPU time | 4.03 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-967484a3-849c-47db-b004-07b1ba4040be |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298008494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1298008494 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1320004016 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 121266747207 ps |
CPU time | 360.7 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:23:46 PM PDT 24 |
Peak memory | 223516 kb |
Host | smart-3147fe9f-3c1a-465d-92fa-224bee18cd01 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320004016 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1320004016 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2403248118 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 239815780 ps |
CPU time | 2.83 seconds |
Started | Jul 18 05:17:41 PM PDT 24 |
Finished | Jul 18 05:17:47 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-b04af867-da90-4513-b738-cebac96456a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403248118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2403248118 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1756133807 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 2692341955 ps |
CPU time | 11.23 seconds |
Started | Jul 18 05:25:59 PM PDT 24 |
Finished | Jul 18 05:26:11 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-d73a8885-552e-4500-9e98-2eaa82d0b4b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756133807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1756133807 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1006678788 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 230489977 ps |
CPU time | 4.1 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:13 PM PDT 24 |
Peak memory | 219116 kb |
Host | smart-94218a38-3a29-4da6-b742-346e274ac1b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006678788 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1006678788 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.523507344 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 197218589 ps |
CPU time | 2.59 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:11 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-5c7ae35a-6cf8-4a7e-bf1e-9a189f6e94d0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523507344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.523507344 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3175363368 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 21674659633 ps |
CPU time | 22.14 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:30 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-2c800a8e-b17b-4978-869b-100aadf97899 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175363368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.3175363368 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2528659821 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 5330994936 ps |
CPU time | 4.18 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:48 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-13b1f161-8c1b-4c1d-bd93-ab5941e03480 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528659821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2 528659821 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1411152424 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 432839919 ps |
CPU time | 1.16 seconds |
Started | Jul 18 05:17:40 PM PDT 24 |
Finished | Jul 18 05:17:45 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-22266ab7-8c71-402c-85df-5475f2acdcf4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411152424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 411152424 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1188244767 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 643510704 ps |
CPU time | 7.79 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:18 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-8c9b91e1-5318-4fe3-9c9f-e8350a44c6a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188244767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1188244767 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1849702342 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 59136483327 ps |
CPU time | 53.35 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:19:01 PM PDT 24 |
Peak memory | 215964 kb |
Host | smart-24a44043-7094-47cc-ab29-cc31726ac22f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849702342 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1849702342 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1007942911 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 82829918 ps |
CPU time | 4.32 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:12 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-4501a732-f242-473c-8353-980ace0b6f77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007942911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1007942911 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3501788315 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 2014567940 ps |
CPU time | 13.93 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:19 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-2bfe42d9-e8a4-4ca5-bc4e-3c68e805dbb8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501788315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3501788315 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.974668710 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 1583287997 ps |
CPU time | 3.4 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 217208 kb |
Host | smart-49df390d-f992-4ef3-8b2f-e2e8a087ce28 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974668710 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.974668710 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2575198261 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 550557559 ps |
CPU time | 2.42 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-0446a597-334d-4e45-800c-a7c4353486d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575198261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2575198261 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1760007197 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 17696120545 ps |
CPU time | 19.08 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:26 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-c01eb755-a463-4211-8605-99ea926bb74c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760007197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1760007197 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1516252719 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 5658895633 ps |
CPU time | 13.5 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:19 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-0ac72eae-6db8-40a1-a6da-663701190f76 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516252719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1 516252719 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1024492767 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 111885716 ps |
CPU time | 0.98 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-fab1bd95-6ca4-4430-9fbe-451c3159a068 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024492767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1 024492767 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1313089537 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 721816485 ps |
CPU time | 3.59 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-a3977e78-1b83-450c-9b6f-55c47dbce82e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313089537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.1313089537 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.230678390 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 25443107613 ps |
CPU time | 24.49 seconds |
Started | Jul 18 05:18:03 PM PDT 24 |
Finished | Jul 18 05:18:28 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-e04a2c10-1ce1-4a8f-9c5a-ac63223d3e8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230678390 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.230678390 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2537846033 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 204592174 ps |
CPU time | 3.62 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-2107cf59-7028-470d-9967-9accbffa548f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537846033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2537846033 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.209180425 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 799460574 ps |
CPU time | 4.26 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:11 PM PDT 24 |
Peak memory | 221816 kb |
Host | smart-09fc75e1-e537-472e-be51-7d7a086a1d48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209180425 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.209180425 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1395874918 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 205085201 ps |
CPU time | 2.37 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:11 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-711e3859-4399-40b1-a8ed-4ba8a0bcba11 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395874918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1395874918 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3728466397 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 17171567286 ps |
CPU time | 13.21 seconds |
Started | Jul 18 05:18:03 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-7cdc7695-a47b-4b50-be5e-e214a9a12aed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728466397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.3728466397 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2636251677 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 3135599432 ps |
CPU time | 1.73 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:07 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-c68a060f-10e2-4e07-b4a4-543fcc3725fb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636251677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2 636251677 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.434394454 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 171901121 ps |
CPU time | 0.8 seconds |
Started | Jul 18 05:18:07 PM PDT 24 |
Finished | Jul 18 05:18:11 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-fc256e1a-0e6c-4d3a-a088-c856a6a8858f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434394454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.434394454 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3034055046 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 216512891 ps |
CPU time | 3.49 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:10 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-c892b143-2c7c-4222-9f02-2cefde2bd9cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034055046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3034055046 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4281539011 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 31463685150 ps |
CPU time | 60.99 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:19:12 PM PDT 24 |
Peak memory | 221984 kb |
Host | smart-8216cbe1-f51b-4a93-9012-8f916f099001 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281539011 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4281539011 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.299508840 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 151261093 ps |
CPU time | 2.62 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:09 PM PDT 24 |
Peak memory | 213884 kb |
Host | smart-ff9d25ef-5536-45ea-a9d8-4d927bb27adb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299508840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.299508840 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.513416179 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 4710606385 ps |
CPU time | 5.36 seconds |
Started | Jul 18 05:18:05 PM PDT 24 |
Finished | Jul 18 05:18:13 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-08b853ab-9b04-4e9a-b60d-04a020df7ae5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513416179 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.513416179 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.234998620 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 132689128 ps |
CPU time | 1.74 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:09 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-bcbb6c2d-3fd7-4871-bf71-aa1938b90d55 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234998620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.234998620 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2290733418 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 20299871217 ps |
CPU time | 17 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:25 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-29fb219b-2050-4a76-b546-8ff0b1120781 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290733418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.2290733418 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3496616345 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 12588587514 ps |
CPU time | 6.8 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-1e8b5ec3-b992-43cc-bf15-36fbd7f462b7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496616345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 496616345 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3425917836 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 348971333 ps |
CPU time | 0.84 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:14 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-83fd9725-a16a-4c81-a9f7-9fa8d0beb4e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425917836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 425917836 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2557443965 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 515056868 ps |
CPU time | 7.69 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-1af060d5-2ffd-4d97-b18e-96933935f8bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557443965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2557443965 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1052533135 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 20923533371 ps |
CPU time | 44.31 seconds |
Started | Jul 18 05:25:15 PM PDT 24 |
Finished | Jul 18 05:26:02 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-19e3616d-9cbe-4e48-991e-e1904dd49153 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052533135 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1052533135 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2737957341 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 183456757 ps |
CPU time | 2.5 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:14 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-33ded8b4-df47-4305-a305-2d9985a20498 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737957341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2737957341 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2419691099 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 1420270420 ps |
CPU time | 11.15 seconds |
Started | Jul 18 05:18:04 PM PDT 24 |
Finished | Jul 18 05:18:16 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-700c7df7-8282-40bf-b40d-3fff6bb90815 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419691099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2419691099 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.980079392 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 3009054920 ps |
CPU time | 2.73 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 217212 kb |
Host | smart-02d46bf0-80ec-4d1f-a2af-1a6cd1bc90fd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980079392 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.980079392 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3207222092 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 330194321 ps |
CPU time | 1.75 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:15 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-4dc591a1-34ab-4edd-b42f-886a5de41322 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207222092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3207222092 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4065696270 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 27267462541 ps |
CPU time | 77.02 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:19:32 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-c89976fb-ff92-4cb6-864b-900ee9373798 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065696270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.4065696270 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2017113482 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1596752099 ps |
CPU time | 2.22 seconds |
Started | Jul 18 05:18:10 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-4fe533dc-4ce3-4cc6-9067-f2e0910a8c33 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017113482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2 017113482 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1186679466 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 195945640 ps |
CPU time | 0.78 seconds |
Started | Jul 18 05:18:06 PM PDT 24 |
Finished | Jul 18 05:18:09 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-93485036-2dd3-4f31-a28f-f20f987368d8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186679466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 186679466 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2059463835 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 263601079 ps |
CPU time | 4.25 seconds |
Started | Jul 18 05:18:08 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-30422c3f-c905-4d37-a5c0-b3b06be9e6f7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059463835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.2059463835 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.142761299 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 56607988566 ps |
CPU time | 21.55 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:34 PM PDT 24 |
Peak memory | 221924 kb |
Host | smart-a7f9c299-e642-4708-b2ea-7dc31215ff77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142761299 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.142761299 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3075311642 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 512786577 ps |
CPU time | 3.42 seconds |
Started | Jul 18 05:18:09 PM PDT 24 |
Finished | Jul 18 05:18:17 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-20611ee1-463b-4ebe-8b9e-9f46eb2232bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075311642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3075311642 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1459001286 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 46456852 ps |
CPU time | 0.78 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:06 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-43d9b78c-ff8d-434b-9672-f349c958ec20 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459001286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1459001286 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2932881027 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1462969871 ps |
CPU time | 3 seconds |
Started | Jul 18 04:46:41 PM PDT 24 |
Finished | Jul 18 04:46:48 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-8ff43b19-12cb-4d49-abd1-239f0776abfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932881027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2932881027 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.592587509 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 11679838712 ps |
CPU time | 9.31 seconds |
Started | Jul 18 04:46:38 PM PDT 24 |
Finished | Jul 18 04:46:51 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-0db3f570-faf7-4be0-a95d-525747c06867 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592587509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.592587509 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.1784182 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 486888964 ps |
CPU time | 1.68 seconds |
Started | Jul 18 04:46:35 PM PDT 24 |
Finished | Jul 18 04:46:38 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-f6fba372-082a-40ae-82d8-1ae455875510 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1784182 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1717923486 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 179641555 ps |
CPU time | 1.31 seconds |
Started | Jul 18 04:46:36 PM PDT 24 |
Finished | Jul 18 04:46:40 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-18b8e40b-40a5-43bb-b1e5-8e9c85f38f22 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717923486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1717923486 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3255487546 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 364071258 ps |
CPU time | 1.05 seconds |
Started | Jul 18 04:46:40 PM PDT 24 |
Finished | Jul 18 04:46:45 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-eebfdc20-68f8-45eb-b47d-61c603aea356 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255487546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3255487546 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.386384495 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 40144608 ps |
CPU time | 0.9 seconds |
Started | Jul 18 04:46:44 PM PDT 24 |
Finished | Jul 18 04:46:47 PM PDT 24 |
Peak memory | 215348 kb |
Host | smart-622a0f93-c5dc-4f97-910a-6473588d2b6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386384495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.386384495 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2480490393 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1316339391 ps |
CPU time | 2.15 seconds |
Started | Jul 18 04:46:41 PM PDT 24 |
Finished | Jul 18 04:46:47 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-c8f8d42b-6bea-4798-a645-d98a9be336bd |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2480490393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.2480490393 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.2608490037 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 419383317 ps |
CPU time | 0.94 seconds |
Started | Jul 18 04:46:45 PM PDT 24 |
Finished | Jul 18 04:46:47 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-7ba38369-32d9-4637-9368-8168ef9d455a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608490037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2608490037 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3013729236 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1413709965 ps |
CPU time | 4.58 seconds |
Started | Jul 18 04:46:39 PM PDT 24 |
Finished | Jul 18 04:46:47 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-c983a2c3-cbb5-4a2e-8857-f07f5fa6214c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013729236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3013729236 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1993959680 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 158400876 ps |
CPU time | 0.84 seconds |
Started | Jul 18 04:46:43 PM PDT 24 |
Finished | Jul 18 04:46:46 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-cfd26dfe-6bf0-4d90-8390-0d11ba067a9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993959680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1993959680 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4084501658 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 180391038 ps |
CPU time | 0.97 seconds |
Started | Jul 18 04:46:46 PM PDT 24 |
Finished | Jul 18 04:46:48 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-5a00a681-7719-4f65-ab87-43ccdf9e9af1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084501658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4084501658 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3912170671 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 674519330 ps |
CPU time | 1.69 seconds |
Started | Jul 18 04:46:44 PM PDT 24 |
Finished | Jul 18 04:46:48 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-bf6d280a-9931-4f5f-9402-9c486695a6b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912170671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3912170671 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1750578562 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 442139723 ps |
CPU time | 1.11 seconds |
Started | Jul 18 04:46:41 PM PDT 24 |
Finished | Jul 18 04:46:46 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-a80237fb-25c9-42e2-82a4-1ba21b11c63b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750578562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1750578562 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2700809495 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 251260485 ps |
CPU time | 1.35 seconds |
Started | Jul 18 04:46:44 PM PDT 24 |
Finished | Jul 18 04:46:48 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-815439e6-4759-407e-8121-f36fa12167ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700809495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2700809495 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3951443085 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 842540718 ps |
CPU time | 0.99 seconds |
Started | Jul 18 04:46:38 PM PDT 24 |
Finished | Jul 18 04:46:43 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-abeeeddb-8c40-4022-b7b4-3f7e9b199a46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951443085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3951443085 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3226543260 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 360792963 ps |
CPU time | 1.24 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:05 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-bc6d24cc-226e-47bf-ad63-d78e95ca7113 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226543260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3226543260 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.3505662450 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 223546143 ps |
CPU time | 0.84 seconds |
Started | Jul 18 04:46:41 PM PDT 24 |
Finished | Jul 18 04:46:45 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-f2b10952-720f-478f-82ff-c765eda4609d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505662450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3505662450 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.3703330418 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 1776241505 ps |
CPU time | 3.46 seconds |
Started | Jul 18 04:46:40 PM PDT 24 |
Finished | Jul 18 04:46:47 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-e19748cc-5ab0-4fa7-afe1-1605641bc481 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703330418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3703330418 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2576323856 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 4702880869 ps |
CPU time | 7.83 seconds |
Started | Jul 18 04:46:40 PM PDT 24 |
Finished | Jul 18 04:46:52 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-624e1ce4-42ed-4d19-95f5-86924017fc51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576323856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2576323856 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.847923223 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 677501661 ps |
CPU time | 2.2 seconds |
Started | Jul 18 04:47:15 PM PDT 24 |
Finished | Jul 18 04:47:19 PM PDT 24 |
Peak memory | 229568 kb |
Host | smart-ae353fb1-38db-4a4b-a37a-1d0603bd5351 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847923223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.847923223 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.1151353234 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 714711299 ps |
CPU time | 2.84 seconds |
Started | Jul 18 04:46:39 PM PDT 24 |
Finished | Jul 18 04:46:46 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-d8f66f2c-e81e-4ae1-8c7a-c27330e68e81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151353234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1151353234 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.2760593410 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 8355181281 ps |
CPU time | 25.29 seconds |
Started | Jul 18 04:46:38 PM PDT 24 |
Finished | Jul 18 04:47:07 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-be0f92ac-1970-450a-a36d-faad9916c89a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760593410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2760593410 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.4228051913 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 89950959 ps |
CPU time | 0.9 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-58a85be6-a678-4b51-a595-cc790a65465e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228051913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4228051913 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1069801853 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 16666106645 ps |
CPU time | 14.32 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:20 PM PDT 24 |
Peak memory | 216568 kb |
Host | smart-ffeec285-1df4-45da-b998-44369b42868f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069801853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1069801853 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2057144274 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 14032197738 ps |
CPU time | 20.29 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:25 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-c963fb31-a4c0-42d9-b7c6-4aea5ca22caf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057144274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2057144274 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.1141039658 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 545959733 ps |
CPU time | 1.53 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:04 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-f9c86660-b8ad-4ba9-8f72-dbb022f0cc5a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141039658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1141039658 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2172319852 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 2147238193 ps |
CPU time | 3.76 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:14 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-f8751fdc-c580-45ed-82cd-791b6d915073 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172319852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2172319852 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3570535967 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 272712656 ps |
CPU time | 1.42 seconds |
Started | Jul 18 04:46:59 PM PDT 24 |
Finished | Jul 18 04:47:01 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-fa30fd0c-6cfd-4738-88de-db8e87889f58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570535967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3570535967 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3657014179 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 154541147 ps |
CPU time | 0.81 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:04 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-dd0d1c9b-8dc4-493c-8a1a-6ae5556dd897 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657014179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3657014179 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3595244660 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 129714161 ps |
CPU time | 0.81 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:14 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-4cb3e2c0-7276-49cf-a9e2-be3b1d1888d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595244660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3595244660 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1337727087 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 4991120396 ps |
CPU time | 4.94 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:15 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-a9e9fed6-106e-447e-97c8-5d8749719e3f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1337727087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.1337727087 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.2740201160 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 391548555 ps |
CPU time | 1.71 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-f3542656-556a-4642-bb34-3865129fd344 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740201160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2740201160 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4017923698 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2003694291 ps |
CPU time | 6.13 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:09 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-e024ac20-e830-4548-96dd-a6f78025fcd4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017923698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4017923698 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.315272925 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 204436104 ps |
CPU time | 0.87 seconds |
Started | Jul 18 04:47:22 PM PDT 24 |
Finished | Jul 18 04:47:24 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-7cdaaacc-e9fc-4986-aef2-b035ab5b6935 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315272925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.315272925 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3577119004 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 444182009 ps |
CPU time | 0.92 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:05 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-2f618342-3200-4756-a1e9-aa2a2670d3f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577119004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3577119004 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.342604610 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1017915036 ps |
CPU time | 2.2 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:08 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-112b19a8-9ded-453f-bd87-97dbebb04662 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342604610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.342604610 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.417969840 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1020050280 ps |
CPU time | 2.66 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:09 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-2df3fcc1-c084-4acf-a2d7-84da1b6290ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417969840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.417969840 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1043697174 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 148358698 ps |
CPU time | 1.04 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:14 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-2b3aca72-29d2-476f-b28b-9a7220637839 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043697174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1043697174 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3856808375 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 442427300 ps |
CPU time | 0.88 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:06 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-865d7f17-4269-41c6-977e-059e5de55c7c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856808375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3856808375 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.710784622 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 624572591 ps |
CPU time | 2.52 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:08 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-69f4668f-7102-4ed5-9442-35031c816c05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710784622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.710784622 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.1169098631 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 164916973 ps |
CPU time | 1.29 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:11 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-19e77cd7-3337-48a3-ae5b-938c3db41c91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169098631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1169098631 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3134359951 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 747360215 ps |
CPU time | 1.18 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:04 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-d6ef9314-4ab4-4f11-90b6-d97eb427d841 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134359951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3134359951 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.1295723183 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 40570347 ps |
CPU time | 0.87 seconds |
Started | Jul 18 04:47:06 PM PDT 24 |
Finished | Jul 18 04:47:10 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-e137f120-3e46-40ba-975a-56240a005150 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1295723183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1295723183 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1992558496 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 1695873956 ps |
CPU time | 3.17 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:13 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-f8bd9eae-299b-4082-b745-99094cb95000 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992558496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1992558496 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.325575922 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 9078035383 ps |
CPU time | 22.38 seconds |
Started | Jul 18 04:46:59 PM PDT 24 |
Finished | Jul 18 04:47:22 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-84937854-2e9e-458c-b8cf-595941fe9cee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325575922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.325575922 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2099567804 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 991352424 ps |
CPU time | 1.54 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-ff2be862-b6b9-4001-a961-c985ea3bc5a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099567804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2099567804 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.3362507228 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 8757371772 ps |
CPU time | 16.19 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-dc036c9a-efa2-4404-a8ca-ed034e67c39d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362507228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3362507228 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1699695533 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 161783113 ps |
CPU time | 0.78 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:22 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-6779e9f1-5bf4-46b2-bf37-8797cfcc72ba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699695533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1699695533 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1095721360 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 12675709388 ps |
CPU time | 36.16 seconds |
Started | Jul 18 04:47:13 PM PDT 24 |
Finished | Jul 18 04:47:51 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-f3bc46af-33cb-4285-9e77-ce80f48c28c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095721360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1095721360 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3837261583 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2622413031 ps |
CPU time | 8.31 seconds |
Started | Jul 18 04:47:12 PM PDT 24 |
Finished | Jul 18 04:47:23 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-3f234ab9-4c1a-42a6-a4bc-e447391f9ca6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3837261583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.3837261583 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3262960790 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 8228360786 ps |
CPU time | 22.53 seconds |
Started | Jul 18 04:47:12 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-5d95d1d7-027d-4b93-b3da-a35b9cbeb40f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262960790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3262960790 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.3481184616 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 4204915734 ps |
CPU time | 3.49 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:22 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-c11ee600-ed3c-4332-aef1-b4bd63b2c9b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481184616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3481184616 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1787761146 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 126870478 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:19 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-fc8874ab-9774-4858-baab-f887e3624ecd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787761146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1787761146 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.926545631 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 31682963025 ps |
CPU time | 23.21 seconds |
Started | Jul 18 04:47:21 PM PDT 24 |
Finished | Jul 18 04:47:46 PM PDT 24 |
Peak memory | 221708 kb |
Host | smart-6003650e-501f-42f9-8395-f5fc4fb912f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926545631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.926545631 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3627578551 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 11636946073 ps |
CPU time | 34.91 seconds |
Started | Jul 18 04:47:19 PM PDT 24 |
Finished | Jul 18 04:47:56 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-9d2ec16f-0e58-40a0-a6fe-592087f32092 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3627578551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3627578551 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2540936079 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1998386039 ps |
CPU time | 6.68 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-08f852dc-cc71-488c-a9f2-756db27e78bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540936079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2540936079 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.2024324055 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 208624065 ps |
CPU time | 0.73 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:22 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-c6f553f8-d85e-4c74-bd51-0286d2c1a24b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024324055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2024324055 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4258105283 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 4712393180 ps |
CPU time | 13.98 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:36 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-d30deac8-6500-4fae-82cf-16ac5370d8c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258105283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4258105283 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1497113876 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 4383478431 ps |
CPU time | 12.77 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:31 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-664682ed-58b4-4d7e-908d-ff010039b1f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1497113876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1497113876 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.43482949 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 8861926276 ps |
CPU time | 25.26 seconds |
Started | Jul 18 04:47:21 PM PDT 24 |
Finished | Jul 18 04:47:48 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-9d71fdf0-4df3-4e44-9a98-55d08adae328 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=43482949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl _access.43482949 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.459994520 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 4503585872 ps |
CPU time | 2.78 seconds |
Started | Jul 18 04:47:21 PM PDT 24 |
Finished | Jul 18 04:47:25 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-e352b116-bb56-450d-a9ed-e29693c20ca1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459994520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.459994520 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.2826480299 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 165444910 ps |
CPU time | 0.75 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:19 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-7a101f8e-6e39-444e-b6e2-dc5c4db743e3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826480299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2826480299 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.166569668 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 5337982036 ps |
CPU time | 16.92 seconds |
Started | Jul 18 04:47:19 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-7d20b230-d66f-4843-97ed-cfeb5bf5ea19 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166569668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.166569668 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1066130618 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 3819234827 ps |
CPU time | 4.05 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:23 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-c2f15273-9a3a-444d-92c5-f489f8732c14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066130618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1066130618 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.24076672 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 2906379163 ps |
CPU time | 1.96 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:24 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-ff5f9f97-062d-4516-bb07-26f2afe31919 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=24076672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl _access.24076672 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.799946251 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 10853968651 ps |
CPU time | 9.15 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:31 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-a0e4cb97-8740-4af3-9152-455d54439803 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799946251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.799946251 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.2274460978 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 3070096514 ps |
CPU time | 3.5 seconds |
Started | Jul 18 04:47:21 PM PDT 24 |
Finished | Jul 18 04:47:26 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-79e38a0b-4cc2-4d4e-aae7-70b4790f6d75 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274460978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2274460978 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.1164157478 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 117999311 ps |
CPU time | 0.74 seconds |
Started | Jul 18 04:47:25 PM PDT 24 |
Finished | Jul 18 04:47:27 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-8c47a254-67c0-4ab5-a8a5-09f3eda563b3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164157478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1164157478 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4006883924 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 4390326164 ps |
CPU time | 4.06 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:26 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-e8b522de-2497-43f9-a027-61e74a98ffee |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4006883924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.4006883924 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.1574899180 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1442681980 ps |
CPU time | 1.27 seconds |
Started | Jul 18 04:47:16 PM PDT 24 |
Finished | Jul 18 04:47:19 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-bd349387-1556-4ba3-8814-dede34cbc34d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574899180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1574899180 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.3685024907 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 8299131080 ps |
CPU time | 11.08 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:32 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-0044a39c-0e3b-4a4e-bb71-6b13528339f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685024907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3685024907 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.2897094911 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 76867345 ps |
CPU time | 0.88 seconds |
Started | Jul 18 04:47:22 PM PDT 24 |
Finished | Jul 18 04:47:25 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-9d7325e6-010c-4b08-b814-0a4754b115ea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897094911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2897094911 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.779828168 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 1388115154 ps |
CPU time | 1.61 seconds |
Started | Jul 18 04:47:18 PM PDT 24 |
Finished | Jul 18 04:47:21 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-81e7f03a-aee3-43f9-98c7-a0d602fe3306 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779828168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.779828168 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2268067230 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 3369998862 ps |
CPU time | 6.29 seconds |
Started | Jul 18 04:47:18 PM PDT 24 |
Finished | Jul 18 04:47:26 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-96ce675d-2f26-4383-8162-14ba19489cef |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2268067230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.2268067230 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.3721438023 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1468165306 ps |
CPU time | 2.31 seconds |
Started | Jul 18 04:47:19 PM PDT 24 |
Finished | Jul 18 04:47:22 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-d809836f-7cdf-4463-9ad4-7ca5734777bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721438023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3721438023 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.46959745 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 4809988779 ps |
CPU time | 9.45 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-f9cb2ba7-2d01-4860-a0ca-88e58fd590c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46959745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.46959745 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3313243833 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 66223559 ps |
CPU time | 0.86 seconds |
Started | Jul 18 04:47:17 PM PDT 24 |
Finished | Jul 18 04:47:20 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-30afd6ee-7ff1-4c3c-9ef0-9d47803f6915 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313243833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3313243833 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.121598669 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 42746712339 ps |
CPU time | 115.39 seconds |
Started | Jul 18 04:47:22 PM PDT 24 |
Finished | Jul 18 04:49:19 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-73c265d2-96f3-405e-98a6-d234519d2ac7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121598669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.121598669 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1052380106 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2088693111 ps |
CPU time | 4.5 seconds |
Started | Jul 18 04:47:19 PM PDT 24 |
Finished | Jul 18 04:47:25 PM PDT 24 |
Peak memory | 205792 kb |
Host | smart-81d77682-502d-497c-b8c1-8c17cf0d9f4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052380106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1052380106 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2654452320 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 5393412397 ps |
CPU time | 15.18 seconds |
Started | Jul 18 04:47:24 PM PDT 24 |
Finished | Jul 18 04:47:41 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-a357550d-511e-4f31-8a9c-2f07c0acddb5 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2654452320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.2654452320 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.5609640 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 7476185022 ps |
CPU time | 6.55 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-ebf73d9d-5243-4f49-9c89-8932abca011e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5609640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.5609640 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.1377280078 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 4794264663 ps |
CPU time | 8.45 seconds |
Started | Jul 18 04:47:24 PM PDT 24 |
Finished | Jul 18 04:47:34 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-71545953-3b5c-4d2e-8bf0-9f465f4eefe5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377280078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1377280078 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3122128709 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 60404213 ps |
CPU time | 0.83 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-68f4562f-059b-414e-8714-200b02c5746a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122128709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3122128709 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3138586799 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 39200237962 ps |
CPU time | 32.73 seconds |
Started | Jul 18 04:47:25 PM PDT 24 |
Finished | Jul 18 04:47:59 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-42339a93-0df1-4bce-97b4-40c57d1db4bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138586799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3138586799 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3538344361 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 7147903412 ps |
CPU time | 9.97 seconds |
Started | Jul 18 04:47:28 PM PDT 24 |
Finished | Jul 18 04:47:39 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-a722180a-4850-46e0-b683-0e853835b2eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538344361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3538344361 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4089328100 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 1845684152 ps |
CPU time | 3.72 seconds |
Started | Jul 18 04:47:24 PM PDT 24 |
Finished | Jul 18 04:47:29 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-4ed0cab8-84af-4bd9-84ba-91c4ea7ded64 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4089328100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.4089328100 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.2973776090 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 3659851379 ps |
CPU time | 9.93 seconds |
Started | Jul 18 04:47:16 PM PDT 24 |
Finished | Jul 18 04:47:27 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-91b1c664-9ed8-4b59-ac6f-11f350fb55c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973776090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2973776090 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.3518306588 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 4181333901 ps |
CPU time | 7.85 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:43 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-bc5e995b-fd20-4b38-9295-3661e0de3e6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518306588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3518306588 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.1021265133 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 338245146 ps |
CPU time | 0.69 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:36 PM PDT 24 |
Peak memory | 204200 kb |
Host | smart-2f40e614-d5f5-4bb9-8fb4-3e5200f6caa3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021265133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1021265133 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.4220674217 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 18801105477 ps |
CPU time | 63.86 seconds |
Started | Jul 18 04:47:28 PM PDT 24 |
Finished | Jul 18 04:48:33 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-feb7578e-a083-47ca-9d3b-e1e604144b76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220674217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.4220674217 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2288831575 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 2922997878 ps |
CPU time | 3.54 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:39 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-41910984-b030-4300-907c-a06dd3360b98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288831575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2288831575 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4081065599 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1656690557 ps |
CPU time | 2.11 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 212776 kb |
Host | smart-da3adfea-8ba9-4927-b43f-0fb4c9a075f1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4081065599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.4081065599 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.2862986810 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 10265121509 ps |
CPU time | 24.13 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:53 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-d50dfe75-a1b4-4a20-a3c0-552b4e1100c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862986810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2862986810 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.751625724 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 228669158 ps |
CPU time | 0.76 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:30 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-f3585ee2-ff64-41f5-837c-2ad475ff4467 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751625724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.751625724 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1420831334 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 6904197628 ps |
CPU time | 17.15 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:46 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-5532b921-1d47-4f39-b611-708d5717b21b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420831334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1420831334 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1833314502 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 3899876188 ps |
CPU time | 11.16 seconds |
Started | Jul 18 04:47:28 PM PDT 24 |
Finished | Jul 18 04:47:41 PM PDT 24 |
Peak memory | 214400 kb |
Host | smart-481aa545-e531-4643-baf6-658e4d552512 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833314502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1833314502 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1351426120 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 1490555988 ps |
CPU time | 4.81 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:40 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-51f71a83-c38f-4526-8390-21446aac46e2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1351426120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.1351426120 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.3700679482 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 6737017739 ps |
CPU time | 15.62 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:51 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-db53b0d1-1d1b-4ec9-88e1-6b8b1bf0cf2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700679482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3700679482 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.2408188530 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 7202097271 ps |
CPU time | 21.34 seconds |
Started | Jul 18 04:47:32 PM PDT 24 |
Finished | Jul 18 04:47:55 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-ef34c9eb-9525-4e35-96ba-f1f6491ccc8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408188530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2408188530 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.1964042753 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 31729314 ps |
CPU time | 0.78 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:08 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-ce4c3208-79df-46c9-99a8-a258b632d149 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964042753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1964042753 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2404726620 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 74959937577 ps |
CPU time | 156.76 seconds |
Started | Jul 18 04:47:14 PM PDT 24 |
Finished | Jul 18 04:49:52 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-ab7c19e4-3e80-4beb-8a9d-ab2780d8813e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404726620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2404726620 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3805534009 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 2301306258 ps |
CPU time | 7.62 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:20 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-338f83f0-cedd-4189-96b9-c9bb0a9ff652 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805534009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3805534009 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1423843363 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3617294917 ps |
CPU time | 4.21 seconds |
Started | Jul 18 04:47:04 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-8cbdf34c-d510-4cb4-b1dc-23883b0e3d3b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1423843363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.1423843363 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.953288746 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 283878125 ps |
CPU time | 1.03 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:07 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-b6cd6dab-09e5-4971-8c2b-63a58af45062 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953288746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.953288746 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.1424794185 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 9780055864 ps |
CPU time | 7.01 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:18 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-49beba57-fe25-41ad-9053-4b923c8e376d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424794185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1424794185 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.136072080 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 350507373 ps |
CPU time | 1.58 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:08 PM PDT 24 |
Peak memory | 228592 kb |
Host | smart-6ed6a67a-373b-4ea2-ad06-ce6e52f91474 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136072080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.136072080 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.3106569007 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 63111023 ps |
CPU time | 0.71 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:29 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-4d726b31-e098-41c5-8cd3-3ad5fc085a28 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106569007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3106569007 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.2152930186 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 90100883 ps |
CPU time | 0.92 seconds |
Started | Jul 18 04:47:23 PM PDT 24 |
Finished | Jul 18 04:47:25 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-173d9674-23ab-493f-9eee-c19823ecbc0e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152930186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2152930186 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.312116197 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 132736405 ps |
CPU time | 1 seconds |
Started | Jul 18 04:47:23 PM PDT 24 |
Finished | Jul 18 04:47:25 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-2107b33f-e492-463f-8eaa-4beffff2c315 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312116197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.312116197 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.2646030747 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 5350736763 ps |
CPU time | 6.03 seconds |
Started | Jul 18 04:47:28 PM PDT 24 |
Finished | Jul 18 04:47:36 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-6ff7828e-a2a8-42d0-b95b-b79d9ee6d02a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646030747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2646030747 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3307813566 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 155547999 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:22 PM PDT 24 |
Finished | Jul 18 04:47:24 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-57a27398-286f-46be-ad53-a89f430533e9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307813566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3307813566 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.2355533145 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 2623189461 ps |
CPU time | 2.91 seconds |
Started | Jul 18 04:47:28 PM PDT 24 |
Finished | Jul 18 04:47:33 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-eb707511-4f6b-42fb-97a8-2a334cec2e86 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355533145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2355533145 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1167489266 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 40005957 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:30 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-6ef0fdbf-8966-42ca-bc8b-11143bd77c87 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167489266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1167489266 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1541030849 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 84126407 ps |
CPU time | 0.73 seconds |
Started | Jul 18 04:47:27 PM PDT 24 |
Finished | Jul 18 04:47:30 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-8e7f9599-1060-4891-97c4-24de8dd96aba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541030849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1541030849 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.404397506 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 144130027 ps |
CPU time | 1.03 seconds |
Started | Jul 18 04:47:25 PM PDT 24 |
Finished | Jul 18 04:47:27 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-da3f4bb5-3d44-4b5b-99ac-3844272c5a8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404397506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.404397506 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.1883210129 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 73408755 ps |
CPU time | 0.7 seconds |
Started | Jul 18 04:47:20 PM PDT 24 |
Finished | Jul 18 04:47:23 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-f04c4154-713e-49f5-bb85-f79d5a3dbc67 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883210129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1883210129 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.1829804663 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 4178791119 ps |
CPU time | 3.09 seconds |
Started | Jul 18 04:47:23 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-765a3400-9d98-4e1b-83d1-05bd3580a26f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829804663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1829804663 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2716211396 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 70411959 ps |
CPU time | 0.73 seconds |
Started | Jul 18 04:47:37 PM PDT 24 |
Finished | Jul 18 04:47:39 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-80e1db58-39ab-4b30-809b-7ad2bab7bb0c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716211396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2716211396 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.2070317315 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 9529047833 ps |
CPU time | 26.74 seconds |
Started | Jul 18 04:47:22 PM PDT 24 |
Finished | Jul 18 04:47:50 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-d4963134-ec34-4450-a656-acc3ce6363df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070317315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2070317315 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.1885491449 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 114272998 ps |
CPU time | 1.01 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:46 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-9a9b78e9-4b80-42e4-b423-752f3be59a78 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885491449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1885491449 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.3041841644 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 7749581697 ps |
CPU time | 12.05 seconds |
Started | Jul 18 04:47:46 PM PDT 24 |
Finished | Jul 18 04:48:00 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-c27f7b00-3057-4659-801c-46dcce6ba73e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041841644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3041841644 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.1441566543 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 93080551 ps |
CPU time | 0.88 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:13 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-d20e413b-404b-4234-aacf-12aec183e9b8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441566543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1441566543 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3834493884 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 6324084450 ps |
CPU time | 6.73 seconds |
Started | Jul 18 04:47:00 PM PDT 24 |
Finished | Jul 18 04:47:08 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-9b7afaf5-2733-4a6e-92af-e02c6c8ba5c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834493884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3834493884 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.944778913 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1866146943 ps |
CPU time | 1.97 seconds |
Started | Jul 18 04:47:04 PM PDT 24 |
Finished | Jul 18 04:47:10 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-db085035-3e49-4ebd-b89c-8fcb2ffaa218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944778913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.944778913 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3572189482 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 15866559721 ps |
CPU time | 47.23 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:50 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-691a9134-9ca6-4e54-9fff-de6a52cfaefb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3572189482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3572189482 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.946877515 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 85264304 ps |
CPU time | 0.89 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:14 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-74fac2f9-01c2-4876-be2d-e206f315a656 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946877515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.946877515 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.1178190935 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 807585888 ps |
CPU time | 1.71 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:09 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-f2732db9-f002-4bfb-8c98-84d074d15f60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178190935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1178190935 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3020771034 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1646066181 ps |
CPU time | 1.28 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:04 PM PDT 24 |
Peak memory | 229660 kb |
Host | smart-3a434b3c-878c-4dfd-840c-41c787467917 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020771034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3020771034 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3201985871 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 4809116298 ps |
CPU time | 13.53 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:23 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-3e385cdb-95ef-4fd1-85f6-c6449457b977 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201985871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3201985871 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.3745994747 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 137933274 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-9c186a43-f106-46ba-b17a-98f07e46da7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745994747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3745994747 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.3490505258 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 6584545638 ps |
CPU time | 10.31 seconds |
Started | Jul 18 04:47:44 PM PDT 24 |
Finished | Jul 18 04:47:55 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-713f1552-c580-4928-b1d7-b446632ac4fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490505258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3490505258 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1004140528 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 49620776 ps |
CPU time | 0.7 seconds |
Started | Jul 18 04:47:39 PM PDT 24 |
Finished | Jul 18 04:47:41 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-be64530a-8de5-40c4-8bcb-8bbe288b246c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004140528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1004140528 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.3579156591 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 41800795 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-56ee1b60-ff3f-4d31-b908-ba8f8e80a8df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579156591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3579156591 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.944488211 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 6849642564 ps |
CPU time | 11.06 seconds |
Started | Jul 18 04:47:41 PM PDT 24 |
Finished | Jul 18 04:47:53 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-ed4b2307-8a93-4a9a-a47e-ffe51b2c798f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944488211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.944488211 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.697342711 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 62804735 ps |
CPU time | 0.81 seconds |
Started | Jul 18 04:47:35 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-8e6383a1-7d94-4cee-9202-725dcff8ba43 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697342711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.697342711 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.3119185367 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 270914004 ps |
CPU time | 0.69 seconds |
Started | Jul 18 04:47:39 PM PDT 24 |
Finished | Jul 18 04:47:41 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-058d8ddc-0e67-4a7a-9f5b-6e6981b782e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119185367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3119185367 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.3597994253 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 4220514487 ps |
CPU time | 2.82 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:50 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-fd45f803-ecbc-4858-9bff-1af9482c0db7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597994253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3597994253 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1316372324 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 29050266 ps |
CPU time | 0.74 seconds |
Started | Jul 18 04:47:42 PM PDT 24 |
Finished | Jul 18 04:47:43 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-6b9a27eb-1c0c-4cf9-b6c6-4f1626c0a0d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316372324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1316372324 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.3099767571 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 7936269747 ps |
CPU time | 17.01 seconds |
Started | Jul 18 04:47:37 PM PDT 24 |
Finished | Jul 18 04:47:55 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-22c26603-ca49-46a4-a73a-bfc70faaeb55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099767571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3099767571 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.3599199144 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 66248273 ps |
CPU time | 0.82 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:48 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-80329c21-723f-485a-9daa-3d9a9d9a545c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599199144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3599199144 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.3285189200 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 184251508 ps |
CPU time | 0.85 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:48 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-693b8f5f-1679-448a-94db-413669525f1f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285189200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3285189200 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.2419138754 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 54858131 ps |
CPU time | 0.75 seconds |
Started | Jul 18 04:47:47 PM PDT 24 |
Finished | Jul 18 04:47:50 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-d714855c-3207-4e4e-9404-ed76e171f58f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419138754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2419138754 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.3362163579 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 4954047661 ps |
CPU time | 4.26 seconds |
Started | Jul 18 04:47:36 PM PDT 24 |
Finished | Jul 18 04:47:41 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-37dde652-b1be-4a60-810d-96c8e0d7d1ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362163579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3362163579 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.466180317 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 79509843 ps |
CPU time | 0.88 seconds |
Started | Jul 18 04:47:33 PM PDT 24 |
Finished | Jul 18 04:47:35 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-cd94292c-10be-44b3-bd30-884699f03da2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466180317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.466180317 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.2523304422 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 33603003 ps |
CPU time | 0.76 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:08 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-a543639c-7b95-46dc-8ab7-1564d564aae9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523304422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2523304422 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1119472602 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 31061407372 ps |
CPU time | 48.64 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:48:01 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-c09aceca-b15e-4c3a-bdbd-dbf53340322e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119472602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1119472602 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4177861866 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 2653815773 ps |
CPU time | 8.19 seconds |
Started | Jul 18 04:47:00 PM PDT 24 |
Finished | Jul 18 04:47:10 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-16b7af8b-a4b6-4b60-b6cc-15f35b7e3050 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177861866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4177861866 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.57271022 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 700267714 ps |
CPU time | 2.83 seconds |
Started | Jul 18 04:47:15 PM PDT 24 |
Finished | Jul 18 04:47:19 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-4f0337d4-d8f6-4693-bcd6-44b27de69320 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=57271022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_ access.57271022 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.61740907 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 102638233 ps |
CPU time | 0.86 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-eeb0a852-2218-4750-887b-b7bb6bb9ee39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61740907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.61740907 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.2939420269 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 5364628033 ps |
CPU time | 5.14 seconds |
Started | Jul 18 04:47:05 PM PDT 24 |
Finished | Jul 18 04:47:14 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-19dde4db-22b5-496b-9c41-0849f67aad8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939420269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2939420269 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.4168859936 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 1140086324 ps |
CPU time | 1.71 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:15 PM PDT 24 |
Peak memory | 229808 kb |
Host | smart-074907a0-7916-49cf-927b-e6fdf15aa101 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168859936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4168859936 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.3820915888 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 29205662 ps |
CPU time | 0.76 seconds |
Started | Jul 18 04:47:46 PM PDT 24 |
Finished | Jul 18 04:47:50 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-e9dba5d9-7add-4044-8a6c-5e2bc8acb352 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820915888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3820915888 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.636039075 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 65339371 ps |
CPU time | 0.69 seconds |
Started | Jul 18 04:47:32 PM PDT 24 |
Finished | Jul 18 04:47:34 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-404f277b-17a7-40d0-b122-44b01ebe8b8b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636039075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.636039075 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.131009112 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 7967323822 ps |
CPU time | 12.18 seconds |
Started | Jul 18 04:47:31 PM PDT 24 |
Finished | Jul 18 04:47:43 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-81ef3472-e423-42ed-b3fe-1320ee881d95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131009112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.131009112 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.1189605061 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 73622542 ps |
CPU time | 0.81 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:46 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-afbbedc6-8ce4-4c6f-9238-9e704aa52765 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189605061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1189605061 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.1415473779 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 3397314497 ps |
CPU time | 5.31 seconds |
Started | Jul 18 04:47:53 PM PDT 24 |
Finished | Jul 18 04:47:59 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-67815a2f-f7bd-4026-a298-25c26edd48ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415473779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1415473779 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1864057556 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 65022588 ps |
CPU time | 0.74 seconds |
Started | Jul 18 04:47:34 PM PDT 24 |
Finished | Jul 18 04:47:36 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-85cc365a-c93f-4542-b589-03b7d53a8a99 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864057556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1864057556 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.4226929745 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 78279283 ps |
CPU time | 0.73 seconds |
Started | Jul 18 04:47:46 PM PDT 24 |
Finished | Jul 18 04:47:50 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-45749c37-5a2e-4663-bfd9-e86c7343fcec |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226929745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4226929745 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.3035782224 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 5736014498 ps |
CPU time | 5.86 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:52 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-b69f862b-b45e-422f-8808-89a9bbb67853 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035782224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3035782224 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.527434731 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 141049215 ps |
CPU time | 0.82 seconds |
Started | Jul 18 04:47:46 PM PDT 24 |
Finished | Jul 18 04:47:48 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-11608821-4323-4185-815e-710aa40966fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527434731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.527434731 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.3284363214 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 3818078934 ps |
CPU time | 5.06 seconds |
Started | Jul 18 04:47:32 PM PDT 24 |
Finished | Jul 18 04:47:38 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-45848c96-fb1a-4eee-8746-555d5fe2110f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284363214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3284363214 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2949192530 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 71209436 ps |
CPU time | 0.72 seconds |
Started | Jul 18 04:47:53 PM PDT 24 |
Finished | Jul 18 04:47:55 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-a5f36ff1-8312-4144-91c8-785c4628c840 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949192530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2949192530 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.954283983 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2434181646 ps |
CPU time | 7.34 seconds |
Started | Jul 18 04:47:45 PM PDT 24 |
Finished | Jul 18 04:47:53 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-2caee8ed-b778-4a6c-a472-2d1fee4b1c33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954283983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.954283983 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.821271606 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 47676512 ps |
CPU time | 0.75 seconds |
Started | Jul 18 04:47:35 PM PDT 24 |
Finished | Jul 18 04:47:37 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-96a7339b-dc57-4114-ab1b-a0844186cdc9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821271606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.821271606 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.1001060124 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 62954706 ps |
CPU time | 0.7 seconds |
Started | Jul 18 04:47:39 PM PDT 24 |
Finished | Jul 18 04:47:40 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-fe8bdbdc-e830-4593-94d9-d798091b3f46 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001060124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1001060124 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.3042049937 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 35097209 ps |
CPU time | 0.83 seconds |
Started | Jul 18 04:47:41 PM PDT 24 |
Finished | Jul 18 04:47:43 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-8e5c33a0-7ee2-4af8-bbd2-791441643dbe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042049937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3042049937 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.4280693672 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 4604270951 ps |
CPU time | 4.74 seconds |
Started | Jul 18 04:47:41 PM PDT 24 |
Finished | Jul 18 04:47:47 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-a783a397-09b9-4752-a030-c78e977b5d6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280693672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.4280693672 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.2626833075 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 32472923 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-a192b9a2-4bc2-4c07-b95e-3407430d9ad9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626833075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2626833075 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3816994779 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 3259053342 ps |
CPU time | 9.72 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:15 PM PDT 24 |
Peak memory | 214952 kb |
Host | smart-01b83607-9190-4875-9533-2d3479952853 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816994779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3816994779 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3088035187 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 1391236804 ps |
CPU time | 3.25 seconds |
Started | Jul 18 04:47:07 PM PDT 24 |
Finished | Jul 18 04:47:13 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-898f205a-bb9f-4ff3-aa4e-64b694c0e057 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088035187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3088035187 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.835302654 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 3095691861 ps |
CPU time | 9.68 seconds |
Started | Jul 18 04:47:01 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-b8f197af-55f3-4ca5-a694-a3a175c0b52d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=835302654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl _access.835302654 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.133605727 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 10487913280 ps |
CPU time | 15.99 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:21 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-cc3086cb-a00c-4498-815e-d519071d1d63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133605727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.133605727 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3116440340 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 43015463 ps |
CPU time | 0.76 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-c219d317-e79d-4c1d-b32e-cf3b371ef64e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116440340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3116440340 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.8071251 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 160407447810 ps |
CPU time | 179.52 seconds |
Started | Jul 18 04:47:00 PM PDT 24 |
Finished | Jul 18 04:50:01 PM PDT 24 |
Peak memory | 221088 kb |
Host | smart-cb0eb23b-b6fa-4ed8-bd81-c4de6e4637e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8071251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.8071251 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1126506947 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 2296369144 ps |
CPU time | 3.43 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:15 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-97a3b0ad-a27b-4f90-b7ba-a0347f8047ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126506947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1126506947 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.447650183 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1343478118 ps |
CPU time | 1.93 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:07 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-0cb7965f-45ab-4fd2-bd75-285f2abd7591 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=447650183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl _access.447650183 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.3175583906 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2072580848 ps |
CPU time | 4.22 seconds |
Started | Jul 18 04:47:04 PM PDT 24 |
Finished | Jul 18 04:47:12 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-93b3aa4b-2488-4f45-a0a4-119d00ccc2a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3175583906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3175583906 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.3339989246 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 139398409 ps |
CPU time | 0.77 seconds |
Started | Jul 18 04:47:11 PM PDT 24 |
Finished | Jul 18 04:47:15 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-271e040c-145c-4d05-a9af-15953c27b8f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339989246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3339989246 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2924905248 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 1702211787 ps |
CPU time | 2.14 seconds |
Started | Jul 18 04:47:11 PM PDT 24 |
Finished | Jul 18 04:47:16 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-b55b58a1-e483-4b9e-a0d6-2cbe6a3469e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924905248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2924905248 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.46859269 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 10479806569 ps |
CPU time | 14.32 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-b4933a04-5872-4bc3-8cef-6a3cf6835df6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=46859269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_ access.46859269 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3246007633 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 12473437696 ps |
CPU time | 9.33 seconds |
Started | Jul 18 04:47:15 PM PDT 24 |
Finished | Jul 18 04:47:26 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-4cc3c74f-3116-437a-8fbb-660f3545da03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246007633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3246007633 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.1513301147 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 3871292576 ps |
CPU time | 11.38 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:17 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-8a5c0e55-a04a-4281-8939-0340e8078bd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513301147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1513301147 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.7923627 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 119615443 ps |
CPU time | 0.73 seconds |
Started | Jul 18 04:47:02 PM PDT 24 |
Finished | Jul 18 04:47:06 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-f26c74ab-7fc1-4a32-a92e-1b300440095d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7923627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.7923627 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1711464898 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 14696387847 ps |
CPU time | 35.93 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:48 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-30bdc5e5-b677-4cb1-914a-49ba794e507c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711464898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1711464898 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2317702167 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 3407703896 ps |
CPU time | 5.66 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:18 PM PDT 24 |
Peak memory | 213496 kb |
Host | smart-c99ee127-3965-4709-957a-3652c8cae046 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317702167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2317702167 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1604138522 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 6740466412 ps |
CPU time | 19.44 seconds |
Started | Jul 18 04:47:10 PM PDT 24 |
Finished | Jul 18 04:47:33 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-318bcfd3-856c-4112-9c32-d258d80e7b55 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1604138522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.1604138522 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.2940779605 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 9265469186 ps |
CPU time | 23.06 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:35 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-23274f8a-d7e7-4d60-8238-c5efeac4b8e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940779605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2940779605 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.3633659563 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 5704943955 ps |
CPU time | 4.32 seconds |
Started | Jul 18 04:47:09 PM PDT 24 |
Finished | Jul 18 04:47:16 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-68219c4e-f6ae-4991-a9e3-778fa16b4cd2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633659563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3633659563 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2931489864 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 84667713 ps |
CPU time | 0.75 seconds |
Started | Jul 18 04:47:12 PM PDT 24 |
Finished | Jul 18 04:47:15 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-25993eec-3bd9-4e36-a427-c961742ffa93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931489864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2931489864 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1805680119 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 5747607953 ps |
CPU time | 16.82 seconds |
Started | Jul 18 04:47:18 PM PDT 24 |
Finished | Jul 18 04:47:36 PM PDT 24 |
Peak memory | 205708 kb |
Host | smart-b837556e-851a-4927-89c9-8c4ad1554401 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805680119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1805680119 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.223580118 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 5028031416 ps |
CPU time | 14.59 seconds |
Started | Jul 18 04:47:08 PM PDT 24 |
Finished | Jul 18 04:47:26 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-6c4dcd35-85a6-494f-a62d-e2f08c778b87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223580118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.223580118 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1026880056 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 1760225481 ps |
CPU time | 2.42 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:09 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-7718af5b-8c7d-4f0d-bee7-0058d23216cd |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1026880056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.1026880056 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.2766672703 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 3824370423 ps |
CPU time | 10.37 seconds |
Started | Jul 18 04:47:03 PM PDT 24 |
Finished | Jul 18 04:47:18 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-49d176aa-5197-4a56-8883-68c9bbcdb911 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766672703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2766672703 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.693217784 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 7162761454 ps |
CPU time | 13.54 seconds |
Started | Jul 18 04:47:12 PM PDT 24 |
Finished | Jul 18 04:47:28 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-c74f9696-6d82-4feb-9e32-4c5477b1455b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693217784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.693217784 |
Directory | /workspace/9.rv_dm_stress_all/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |