Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.12 95.77 81.66 89.91 75.00 86.50 97.90 55.12


Total tests in report: 441
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.13 62.13 87.73 87.73 61.38 61.38 65.34 65.34 52.50 52.50 69.17 69.17 93.48 93.48 5.30 5.30 /workspace/coverage/default/40.rv_dm_stress_all.1051459370
67.92 5.79 87.78 0.05 64.83 3.45 68.09 2.75 60.00 7.50 70.17 1.00 94.64 1.16 29.96 24.66 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3970997435
73.14 5.21 91.10 3.32 69.79 4.97 78.30 10.21 70.00 10.00 75.83 5.67 96.11 1.47 30.83 0.86 /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3058918098
76.19 3.06 92.45 1.36 72.55 2.76 86.51 8.20 75.00 5.00 79.17 3.33 96.11 0.00 31.57 0.74 /workspace/coverage/default/43.rv_dm_stress_all.3515594810
79.09 2.90 92.66 0.20 75.03 2.48 87.49 0.98 75.00 0.00 80.00 0.83 96.21 0.11 47.23 15.66 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1556217474
79.55 0.47 92.91 0.25 76.14 1.10 87.65 0.16 75.00 0.00 81.00 1.00 96.21 0.00 47.97 0.74 /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1242593291
80.01 0.45 92.91 0.00 76.14 0.00 87.65 0.00 75.00 0.00 81.00 0.00 97.16 0.95 50.18 2.22 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1914209729
80.43 0.42 93.36 0.45 77.10 0.97 88.31 0.66 75.00 0.00 81.50 0.50 97.16 0.00 50.55 0.37 /workspace/coverage/default/1.rv_dm_alert_test.4051599161
80.73 0.30 93.96 0.60 77.79 0.69 88.31 0.00 75.00 0.00 82.33 0.83 97.16 0.00 50.55 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.530946344
80.97 0.24 94.27 0.30 78.48 0.69 88.39 0.08 75.00 0.00 82.83 0.50 97.16 0.00 50.68 0.12 /workspace/coverage/default/1.rv_dm_debug_disabled.2245434918
81.21 0.24 94.27 0.00 79.17 0.69 88.68 0.29 75.00 0.00 83.17 0.33 97.16 0.00 51.05 0.37 /workspace/coverage/default/36.rv_dm_stress_all.704689741
81.39 0.17 94.57 0.30 79.59 0.41 88.68 0.00 75.00 0.00 83.67 0.50 97.16 0.00 51.05 0.00 /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3455241883
81.53 0.14 94.57 0.00 80.00 0.41 88.93 0.25 75.00 0.00 83.67 0.00 97.27 0.11 51.29 0.25 /workspace/coverage/default/1.rv_dm_sec_cm.3997600132
81.68 0.14 94.87 0.30 80.00 0.00 89.01 0.08 75.00 0.00 84.17 0.50 97.27 0.00 51.42 0.12 /workspace/coverage/default/0.rv_dm_abstractcmd_status.42282107
81.82 0.14 94.87 0.00 80.00 0.00 89.01 0.00 75.00 0.00 84.17 0.00 97.27 0.00 52.40 0.99 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4054298860
81.95 0.13 95.02 0.15 80.14 0.14 89.09 0.08 75.00 0.00 84.33 0.17 97.27 0.00 52.77 0.37 /workspace/coverage/default/18.rv_dm_stress_all.4095468433
82.05 0.11 95.02 0.00 80.14 0.00 89.42 0.33 75.00 0.00 84.33 0.00 97.69 0.42 52.77 0.00 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3917616303
82.16 0.11 95.12 0.10 80.28 0.14 89.42 0.00 75.00 0.00 84.83 0.50 97.69 0.00 52.77 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.630212822
82.26 0.10 95.27 0.15 80.41 0.14 89.42 0.00 75.00 0.00 85.00 0.17 97.69 0.00 53.02 0.25 /workspace/coverage/default/24.rv_dm_stress_all.4148471015
82.35 0.09 95.32 0.05 80.83 0.41 89.42 0.00 75.00 0.00 85.17 0.17 97.69 0.00 53.02 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3219219449
82.43 0.08 95.47 0.15 80.97 0.14 89.42 0.00 75.00 0.00 85.33 0.17 97.69 0.00 53.14 0.12 /workspace/coverage/default/39.rv_dm_stress_all.3050895688
82.51 0.08 95.47 0.00 80.97 0.00 89.62 0.21 75.00 0.00 85.33 0.00 97.69 0.00 53.51 0.37 /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2047545091
82.59 0.08 95.47 0.00 81.24 0.28 89.62 0.00 75.00 0.00 85.50 0.17 97.69 0.00 53.64 0.12 /workspace/coverage/default/1.rv_dm_progbuf_busy.3567094373
82.66 0.06 95.57 0.10 81.24 0.00 89.62 0.00 75.00 0.00 85.83 0.33 97.69 0.00 53.64 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1021888672
82.71 0.05 95.62 0.05 81.38 0.14 89.62 0.00 75.00 0.00 86.00 0.17 97.69 0.00 53.64 0.00 /workspace/coverage/default/0.rv_dm_hartsel_warl.3699689082
82.76 0.05 95.67 0.05 81.52 0.14 89.62 0.00 75.00 0.00 86.17 0.17 97.69 0.00 53.64 0.00 /workspace/coverage/default/37.rv_dm_stress_all.2550225067
82.79 0.04 95.67 0.00 81.52 0.00 89.66 0.04 75.00 0.00 86.17 0.00 97.90 0.21 53.64 0.00 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4264590363
82.83 0.04 95.67 0.00 81.52 0.00 89.66 0.00 75.00 0.00 86.17 0.00 97.90 0.00 53.88 0.25 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1983366694
82.86 0.04 95.67 0.00 81.52 0.00 89.66 0.00 75.00 0.00 86.17 0.00 97.90 0.00 54.13 0.25 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2843269153
82.90 0.04 95.67 0.00 81.52 0.00 89.66 0.00 75.00 0.00 86.17 0.00 97.90 0.00 54.38 0.25 /workspace/coverage/default/11.rv_dm_stress_all.2604392237
82.93 0.04 95.67 0.00 81.52 0.00 89.66 0.00 75.00 0.00 86.17 0.00 97.90 0.00 54.62 0.25 /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.361390959
82.97 0.04 95.67 0.00 81.52 0.00 89.79 0.12 75.00 0.00 86.17 0.00 97.90 0.00 54.75 0.12 /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4130415147
83.00 0.03 95.72 0.05 81.52 0.00 89.79 0.00 75.00 0.00 86.33 0.17 97.90 0.00 54.75 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2788479904
83.03 0.03 95.77 0.05 81.52 0.00 89.79 0.00 75.00 0.00 86.50 0.17 97.90 0.00 54.75 0.00 /workspace/coverage/default/26.rv_dm_stress_all.1442262661
83.05 0.02 95.77 0.00 81.66 0.14 89.79 0.00 75.00 0.00 86.50 0.00 97.90 0.00 54.75 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.133836142
83.07 0.02 95.77 0.00 81.66 0.00 89.79 0.00 75.00 0.00 86.50 0.00 97.90 0.00 54.87 0.12 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.99724967
83.09 0.02 95.77 0.00 81.66 0.00 89.79 0.00 75.00 0.00 86.50 0.00 97.90 0.00 54.99 0.12 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2868957980
83.10 0.02 95.77 0.00 81.66 0.00 89.79 0.00 75.00 0.00 86.50 0.00 97.90 0.00 55.12 0.12 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2764525408
83.12 0.01 95.77 0.00 81.66 0.00 89.87 0.08 75.00 0.00 86.50 0.00 97.90 0.00 55.12 0.00 /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1984574333
83.12 0.01 95.77 0.00 81.66 0.00 89.91 0.04 75.00 0.00 86.50 0.00 97.90 0.00 55.12 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.347957820

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1206353959
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2760485398
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2861975080
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3106115857
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2708341175
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3574921133
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.588925112
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.894392178
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3103024876
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1485370096
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1951392708
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1257315548
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.68693125
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.118846223
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.711438617
/workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4282334259
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1326914855
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.39512403
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2808524835
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.588503042
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4261716937
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3157050620
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2298726200
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1484531181
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1120724282
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2588818186
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3973747288
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1820479685
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3233786029
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1639317782
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2045536110
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2928895656
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4195259327
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1180186801
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1296635237
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.677620429
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1072139446
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3891210585
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.367535797
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2703410058
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.889309553
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4188669000
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2732997754
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.519633703
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3613604672
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2576788896
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.432695956
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.134137184
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2397394181
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.493411063
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3460058749
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.129851027
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1677744197
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.951920868
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1091012373
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1005999401
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3010318501
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2527229650
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3014301721
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2870840859
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1228606794
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2570293520
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1430322469
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.998698706
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4195635505
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3603135310
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.893777716
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2677437451
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2187928360
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.524132401
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1249309111
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.256711546
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.993958725
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2722862726
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.524429552
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3698755457
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.583630729
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3982878849
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3557548545
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3522220042
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.23391768
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1163134072
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1794152238
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3185459527
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4263271000
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1324326903
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.279486016
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3517414173
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.432967289
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3861915274
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1151400426
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2960662322
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3254200167
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.470759138
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1823727957
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2026785933
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1804238153
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3822713538
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3783713720
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3628501884
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.864147593
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1327826207
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1627455422
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.106770777
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2839021178
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2575572576
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3676618036
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1466940334
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4211101552
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.463837419
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1410970117
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2958656358
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.916150984
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2645184867
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4216392969
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2194433339
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4058785451
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3341481047
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.47385610
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.698076133
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3787545212
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.553118581
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.527611484
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4265222271
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1251532133
/workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1512433266
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3337889640
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4089933444
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.363230525
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2934165645
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3163686717
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1086096315
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1056194531
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2199659292
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4140433213
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2559148902
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2613760435
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3778125934
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1899133885
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3877847779
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2824297148
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4019878007
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.579069564
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/workspace/coverage/default/3.rv_dm_alert_test.1441566543
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/workspace/coverage/default/37.rv_dm_alert_test.3285189200
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/workspace/coverage/default/6.rv_dm_alert_test.3116440340
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/workspace/coverage/default/9.rv_dm_stress_all.693217784



Total test records in report: 441
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.rv_dm_sba_tl_access.325575922 Jul 18 04:46:59 PM PDT 24 Jul 18 04:47:22 PM PDT 24 9078035383 ps
T2 /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2480490393 Jul 18 04:46:41 PM PDT 24 Jul 18 04:46:47 PM PDT 24 1316339391 ps
T3 /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.944778913 Jul 18 04:47:04 PM PDT 24 Jul 18 04:47:10 PM PDT 24 1866146943 ps
T4 /workspace/coverage/default/34.rv_dm_stress_all.3597994253 Jul 18 04:47:45 PM PDT 24 Jul 18 04:47:50 PM PDT 24 4220514487 ps
T35 /workspace/coverage/default/1.rv_dm_alert_test.4051599161 Jul 18 04:47:01 PM PDT 24 Jul 18 04:47:04 PM PDT 24 53277957 ps
T40 /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.24076672 Jul 18 04:47:20 PM PDT 24 Jul 18 04:47:24 PM PDT 24 2906379163 ps
T5 /workspace/coverage/default/40.rv_dm_stress_all.1051459370 Jul 18 04:47:33 PM PDT 24 Jul 18 04:47:39 PM PDT 24 4749066587 ps
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T265 /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.166569668 Jul 18 04:47:19 PM PDT 24 Jul 18 04:47:37 PM PDT 24 5337982036 ps
T44 /workspace/coverage/default/2.rv_dm_sec_cm.136072080 Jul 18 04:47:03 PM PDT 24 Jul 18 04:47:08 PM PDT 24 350507373 ps
T66 /workspace/coverage/default/32.rv_dm_alert_test.3579156591 Jul 18 04:47:34 PM PDT 24 Jul 18 04:47:37 PM PDT 24 41800795 ps
T67 /workspace/coverage/default/8.rv_dm_alert_test.7923627 Jul 18 04:47:02 PM PDT 24 Jul 18 04:47:06 PM PDT 24 119615443 ps
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T88 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.347957820 Jul 18 05:17:39 PM PDT 24 Jul 18 05:17:45 PM PDT 24 208560674 ps
T80 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1466940334 Jul 18 05:18:09 PM PDT 24 Jul 18 05:18:16 PM PDT 24 503241266 ps
T298 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3157050620 Jul 18 05:17:38 PM PDT 24 Jul 18 05:19:36 PM PDT 24 41494827650 ps
T81 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2570293520 Jul 18 05:18:14 PM PDT 24 Jul 18 05:18:21 PM PDT 24 1373220838 ps
T89 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.974668710 Jul 18 05:18:08 PM PDT 24 Jul 18 05:18:15 PM PDT 24 1583287997 ps
T74 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3970997435 Jul 18 05:17:39 PM PDT 24 Jul 18 05:19:01 PM PDT 24 27662060451 ps
T90 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.980079392 Jul 18 05:18:09 PM PDT 24 Jul 18 05:18:17 PM PDT 24 3009054920 ps
T76 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2870840859 Jul 18 05:18:25 PM PDT 24 Jul 18 05:18:30 PM PDT 24 102344245 ps
T299 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3822713538 Jul 18 05:18:04 PM PDT 24 Jul 18 05:18:39 PM PDT 24 13747638826 ps
T96 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.523507344 Jul 18 05:18:07 PM PDT 24 Jul 18 05:18:11 PM PDT 24 197218589 ps
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