Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331840	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	677042	1		T4	8		T7	6		T9	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	525239	1		T4	8		T7	6		T10	80
values[0x0]	189998	1		T4	13		T7	3		T9	1
values[0x1]	293645	1		T4	5		T7	5		T9	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202566	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	806316	1		T4	9		T7	8		T9	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3623	1		T14	2		T15	1		T38	2
valid_sources[0x01]	3649	1		T23	1		T26	1		T138	4
valid_sources[0x02]	3556	1		T63	29		T61	5		T87	24
valid_sources[0x03]	3560	1		T163	2		T63	33		T61	6
valid_sources[0x04]	3965	1		T38	3		T63	26		T61	2
valid_sources[0x05]	4036	1		T163	1		T63	20		T61	2
valid_sources[0x06]	4215	1		T25	1		T63	19		T61	5
valid_sources[0x07]	3685	1		T26	1		T164	1		T63	31
valid_sources[0x08]	3712	1		T8	3		T165	2		T63	26
valid_sources[0x09]	4613	1		T7	3		T165	1		T63	22
valid_sources[0x0a]	3369	1		T26	4		T63	33		T61	4
valid_sources[0x0b]	4104	1		T164	3		T63	23		T61	5
valid_sources[0x0c]	3770	1		T166	1		T63	18		T61	4
valid_sources[0x0d]	3966	1		T10	1		T131	4		T163	1
valid_sources[0x0e]	3719	1		T14	3		T38	2		T63	24
valid_sources[0x0f]	3657	1		T163	1		T63	18		T61	1
valid_sources[0x10]	4036	1		T6	1		T26	1		T63	21
valid_sources[0x11]	3938	1		T8	3		T131	1		T63	18
valid_sources[0x12]	3963	1		T131	1		T63	22		T61	7
valid_sources[0x13]	4214	1		T10	4		T131	1		T40	1
valid_sources[0x14]	4305	1		T25	2		T13	1		T38	2
valid_sources[0x15]	3606	1		T63	19		T61	2		T58	22
valid_sources[0x16]	3524	1		T131	1		T63	21		T61	3
valid_sources[0x17]	4303	1		T133	2		T136	2		T40	1
valid_sources[0x18]	3744	1		T6	1		T63	27		T61	8
valid_sources[0x19]	4122	1		T10	2		T34	1		T131	2
valid_sources[0x1a]	4314	1		T63	19		T61	5		T87	23
valid_sources[0x1b]	4538	1		T6	2		T63	23		T61	4
valid_sources[0x1c]	3753	1		T167	2		T63	21		T61	1
valid_sources[0x1d]	3223	1		T8	2		T63	30		T61	2
valid_sources[0x1e]	4106	1		T63	24		T61	2		T58	1
valid_sources[0x1f]	4268	1		T15	1		T26	1		T164	1
valid_sources[0x20]	3421	1		T168	1		T63	18		T61	4
valid_sources[0x21]	3832	1		T7	3		T38	2		T63	30
valid_sources[0x22]	5323	1		T63	15		T61	3		T58	33
valid_sources[0x23]	3397	1		T17	6		T63	24		T61	2
valid_sources[0x24]	5029	1		T164	1		T63	18		T61	2
valid_sources[0x25]	3459	1		T143	1		T63	19		T61	3
valid_sources[0x26]	3955	1		T23	1		T63	34		T61	7
valid_sources[0x27]	3751	1		T10	11		T63	26		T61	9
valid_sources[0x28]	3878	1		T8	2		T42	1		T133	2
valid_sources[0x29]	3510	1		T133	1		T20	28		T63	20
valid_sources[0x2a]	4488	1		T15	1		T38	2		T63	25
valid_sources[0x2b]	4102	1		T7	2		T63	25		T61	4
valid_sources[0x2c]	4823	1		T165	1		T63	14		T61	4
valid_sources[0x2d]	3546	1		T63	17		T61	6		T58	27
valid_sources[0x2e]	3532	1		T38	4		T63	26		T61	3
valid_sources[0x2f]	3857	1		T124	2		T26	1		T63	22
valid_sources[0x30]	4542	1		T6	1		T165	1		T164	2
valid_sources[0x31]	3509	1		T63	29		T61	7		T87	23
valid_sources[0x32]	3586	1		T42	3		T131	1		T25	1
valid_sources[0x33]	4468	1		T26	1		T63	14		T61	5
valid_sources[0x34]	3719	1		T4	1		T165	3		T63	24
valid_sources[0x35]	3400	1		T26	1		T63	24		T61	4
valid_sources[0x36]	3140	1		T167	1		T63	29		T61	4
valid_sources[0x37]	4284	1		T131	1		T63	28		T61	2
valid_sources[0x38]	4479	1		T169	5		T38	1		T63	23
valid_sources[0x39]	3858	1		T7	1		T131	2		T23	1
valid_sources[0x3a]	3757	1		T7	4		T41	2		T167	1
valid_sources[0x3b]	3718	1		T13	1		T63	22		T61	2
valid_sources[0x3c]	3840	1		T4	1		T26	1		T63	27
valid_sources[0x3d]	4425	1		T4	1		T40	1		T63	22
valid_sources[0x3e]	4342	1		T6	1		T143	1		T63	22
valid_sources[0x3f]	3601	1		T26	3		T164	1		T63	27
valid_sources[0x40]	4152	1		T19	3		T26	3		T63	26
valid_sources[0x41]	3413	1		T6	1		T38	1		T63	17
valid_sources[0x42]	3896	1		T166	1		T38	6		T63	19
valid_sources[0x43]	3416	1		T63	27		T61	3		T58	29
valid_sources[0x44]	4334	1		T15	1		T163	1		T165	1
valid_sources[0x45]	4074	1		T131	1		T167	2		T26	1
valid_sources[0x46]	3588	1		T6	1		T136	1		T170	5
valid_sources[0x47]	3669	1		T10	3		T170	7		T63	26
valid_sources[0x48]	4373	1		T26	1		T63	35		T61	1
valid_sources[0x49]	4217	1		T8	2		T15	1		T23	1
valid_sources[0x4a]	3462	1		T26	1		T28	40		T63	29
valid_sources[0x4b]	3736	1		T26	1		T63	26		T61	2
valid_sources[0x4c]	3791	1		T4	3		T131	2		T63	27
valid_sources[0x4d]	4368	1		T133	2		T26	1		T38	1
valid_sources[0x4e]	3772	1		T4	1		T10	3		T143	2
valid_sources[0x4f]	4013	1		T25	2		T63	15		T61	10
valid_sources[0x50]	3601	1		T63	29		T61	5		T58	45
valid_sources[0x51]	3776	1		T63	24		T61	3		T58	38
valid_sources[0x52]	4320	1		T8	1		T6	1		T133	1
valid_sources[0x53]	4118	1		T6	1		T165	1		T63	24
valid_sources[0x54]	4069	1		T171	8		T63	22		T61	3
valid_sources[0x55]	3756	1		T131	1		T63	31		T61	2
valid_sources[0x56]	4807	1		T165	1		T63	25		T64	140
valid_sources[0x57]	3806	1		T14	5		T165	1		T63	31
valid_sources[0x58]	3728	1		T133	1		T63	24		T61	8
valid_sources[0x59]	3349	1		T40	1		T63	32		T61	4
valid_sources[0x5a]	3208	1		T23	1		T26	1		T143	1
valid_sources[0x5b]	4186	1		T167	2		T143	1		T63	19
valid_sources[0x5c]	4446	1		T14	1		T41	2		T63	21
valid_sources[0x5d]	4065	1		T63	17		T61	4		T58	24
valid_sources[0x5e]	3988	1		T25	1		T143	2		T63	32
valid_sources[0x5f]	3342	1		T23	1		T63	18		T61	4
valid_sources[0x60]	3690	1		T8	4		T38	4		T63	25
valid_sources[0x61]	3954	1		T26	3		T63	19		T61	4
valid_sources[0x62]	3137	1		T172	18		T25	7		T171	1
valid_sources[0x63]	4445	1		T4	3		T17	2		T26	1
valid_sources[0x64]	4417	1		T18	1		T135	14		T63	24
valid_sources[0x65]	4124	1		T131	1		T26	1		T38	4
valid_sources[0x66]	4321	1		T63	12		T61	3		T87	24
valid_sources[0x67]	3562	1		T63	25		T61	4		T58	88
valid_sources[0x68]	4521	1		T63	24		T61	4		T87	20
valid_sources[0x69]	3779	1		T63	14		T61	4		T87	20
valid_sources[0x6a]	3428	1		T23	1		T63	16		T61	6
valid_sources[0x6b]	4482	1		T19	3		T24	3		T26	1
valid_sources[0x6c]	3949	1		T18	1		T40	2		T63	31
valid_sources[0x6d]	3841	1		T133	1		T23	3		T41	5
valid_sources[0x6e]	3965	1		T8	1		T20	2		T63	27
valid_sources[0x6f]	3669	1		T7	1		T63	25		T61	2
valid_sources[0x70]	4038	1		T6	1		T26	3		T164	3
valid_sources[0x71]	4261	1		T13	1		T26	1		T63	30
valid_sources[0x72]	3893	1		T6	1		T171	1		T165	1
valid_sources[0x73]	4602	1		T8	1		T165	1		T63	32
valid_sources[0x74]	5010	1		T63	26		T61	1		T58	27
valid_sources[0x75]	3584	1		T6	1		T40	1		T63	26
valid_sources[0x76]	3484	1		T173	2		T145	12		T63	24
valid_sources[0x77]	3936	1		T17	1		T36	23		T63	27
valid_sources[0x78]	3547	1		T17	1		T13	1		T63	14
valid_sources[0x79]	3602	1		T15	2		T165	1		T63	32
valid_sources[0x7a]	3448	1		T131	1		T41	1		T168	1
valid_sources[0x7b]	3657	1		T19	1		T13	4		T63	30
valid_sources[0x7c]	3587	1		T21	3		T15	1		T38	1
valid_sources[0x7d]	4307	1		T63	24		T64	554		T61	4
valid_sources[0x7e]	4171	1		T10	3		T170	6		T13	6
valid_sources[0x7f]	4758	1		T63	23		T61	14		T58	17
valid_sources[0x80]	3900	1		T169	2		T63	22		T61	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

322663

1

T4

2

T7

3

T10

80

values[0x0]

all_enables

biggest_size

177649

1

T4

4

T7

3

T9

1

values[0x1]

all_enables

biggest_size

176730

1

T4

2

T8

4

T17

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11602	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	174600	1		T1	10		T2	2		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50596	1		T63	21		T64	6		T61	94
values[0x0]	65815	1		T1	5		T2	2		T3	4
values[0x1]	69791	1		T1	5		T2	3		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7055	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	179147	1		T1	10		T2	2		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	777	1		T170	1		T26	1		T174	1
valid_sources[0x01]	758	1		T47	1		T175	1		T176	1
valid_sources[0x02]	549	1		T61	1		T62	1		T81	1
valid_sources[0x03]	715	1		T27	1		T23	1		T61	3
valid_sources[0x04]	704	1		T177	1		T178	1		T131	1
valid_sources[0x05]	898	1		T179	1		T180	1		T61	3
valid_sources[0x06]	603	1		T181	4		T81	1		T88	3
valid_sources[0x07]	700	1		T179	1		T150	1		T61	1
valid_sources[0x08]	701	1		T45	1		T182	1		T183	1
valid_sources[0x09]	642	1		T67	1		T184	4		T59	3
valid_sources[0x0a]	570	1		T134	1		T180	1		T185	1
valid_sources[0x0b]	647	1		T4	6		T186	1		T187	1
valid_sources[0x0c]	812	1		T32	1		T188	1		T134	1
valid_sources[0x0d]	894	1		T68	1		T163	1		T139	1
valid_sources[0x0e]	924	1		T71	2		T189	1		T190	1
valid_sources[0x0f]	990	1		T2	1		T191	2		T192	1
valid_sources[0x10]	603	1		T27	1		T193	1		T26	1
valid_sources[0x11]	694	1		T59	4		T90	1		T75	299
valid_sources[0x12]	686	1		T193	1		T58	2		T62	1
valid_sources[0x13]	729	1		T1	3		T123	7		T194	1
valid_sources[0x14]	624	1		T179	1		T25	2		T61	3
valid_sources[0x15]	565	1		T186	2		T195	1		T61	2
valid_sources[0x16]	673	1		T44	1		T28	1		T61	2
valid_sources[0x17]	760	1		T45	3		T8	1		T63	10
valid_sources[0x18]	716	1		T58	3		T87	3		T81	2
valid_sources[0x19]	864	1		T190	1		T183	1		T62	5
valid_sources[0x1a]	686	1		T196	3		T61	2		T62	3
valid_sources[0x1b]	807	1		T197	1		T198	4		T132	1
valid_sources[0x1c]	648	1		T6	10		T185	1		T199	3
valid_sources[0x1d]	621	1		T8	1		T200	1		T201	1
valid_sources[0x1e]	796	1		T3	3		T37	1		T61	1
valid_sources[0x1f]	664	1		T131	2		T202	1		T61	3
valid_sources[0x20]	878	1		T203	4		T64	1		T61	3
valid_sources[0x21]	963	1		T176	1		T174	3		T61	5
valid_sources[0x22]	634	1		T61	5		T88	1		T59	3
valid_sources[0x23]	612	1		T186	1		T204	4		T58	3
valid_sources[0x24]	596	1		T8	1		T205	1		T142	1
valid_sources[0x25]	582	1		T206	1		T62	5		T81	2
valid_sources[0x26]	739	1		T194	1		T28	1		T182	1
valid_sources[0x27]	720	1		T62	4		T81	1		T88	5
valid_sources[0x28]	815	1		T188	1		T61	1		T62	1
valid_sources[0x29]	627	1		T20	1		T62	1		T88	5
valid_sources[0x2a]	849	1		T55	1		T68	1		T169	1
valid_sources[0x2b]	754	1		T71	1		T61	1		T62	2
valid_sources[0x2c]	828	1		T180	2		T165	7		T181	1
valid_sources[0x2d]	671	1		T145	1		T62	9		T81	2
valid_sources[0x2e]	1049	1		T207	2		T176	4		T61	2
valid_sources[0x2f]	558	1		T182	1		T81	2		T88	3
valid_sources[0x30]	740	1		T190	1		T61	1		T62	1
valid_sources[0x31]	600	1		T177	1		T64	1		T58	1
valid_sources[0x32]	652	1		T61	3		T62	2		T88	4
valid_sources[0x33]	791	1		T12	1		T26	1		T61	4
valid_sources[0x34]	885	1		T208	3		T59	5		T75	292
valid_sources[0x35]	601	1		T202	1		T61	2		T88	2
valid_sources[0x36]	1039	1		T209	8		T170	1		T183	1
valid_sources[0x37]	646	1		T5	1		T163	1		T81	2
valid_sources[0x38]	782	1		T61	1		T81	3		T88	1
valid_sources[0x39]	547	1		T33	1		T47	2		T25	1
valid_sources[0x3a]	750	1		T194	3		T210	4		T152	5
valid_sources[0x3b]	767	1		T64	1		T61	1		T62	1
valid_sources[0x3c]	716	1		T68	1		T211	1		T212	1
valid_sources[0x3d]	715	1		T213	1		T61	2		T81	3
valid_sources[0x3e]	763	1		T179	2		T198	1		T13	3
valid_sources[0x3f]	763	1		T131	1		T163	1		T214	1
valid_sources[0x40]	870	1		T61	2		T62	2		T81	1
valid_sources[0x41]	694	1		T215	1		T61	2		T81	1
valid_sources[0x42]	845	1		T147	1		T61	2		T88	4
valid_sources[0x43]	669	1		T8	1		T12	1		T20	2
valid_sources[0x44]	593	1		T54	4		T183	1		T61	1
valid_sources[0x45]	749	1		T211	1		T72	1		T198	1
valid_sources[0x46]	847	1		T216	1		T175	4		T174	1
valid_sources[0x47]	970	1		T177	1		T193	1		T183	2
valid_sources[0x48]	615	1		T62	2		T81	1		T88	3
valid_sources[0x49]	639	1		T182	1		T199	1		T61	1
valid_sources[0x4a]	646	1		T170	1		T192	1		T28	2
valid_sources[0x4b]	581	1		T140	1		T217	1		T61	3
valid_sources[0x4c]	734	1		T177	1		T195	3		T218	10
valid_sources[0x4d]	795	1		T46	1		T219	1		T61	2
valid_sources[0x4e]	718	1		T61	1		T81	2		T88	2
valid_sources[0x4f]	641	1		T61	5		T58	3		T62	3
valid_sources[0x50]	873	1		T185	1		T143	1		T28	1
valid_sources[0x51]	722	1		T4	2		T76	1		T220	1
valid_sources[0x52]	537	1		T61	3		T88	4		T59	3
valid_sources[0x53]	677	1		T188	1		T61	1		T62	1
valid_sources[0x54]	583	1		T181	1		T61	1		T81	1
valid_sources[0x55]	1441	1		T211	1		T61	2		T62	3
valid_sources[0x56]	751	1		T12	1		T167	1		T221	1
valid_sources[0x57]	659	1		T222	3		T200	1		T208	1
valid_sources[0x58]	578	1		T167	1		T61	2		T58	1
valid_sources[0x59]	763	1		T58	1		T87	3		T62	2
valid_sources[0x5a]	614	1		T61	2		T81	1		T88	2
valid_sources[0x5b]	746	1		T143	1		T20	2		T61	2
valid_sources[0x5c]	730	1		T177	1		T129	6		T58	8
valid_sources[0x5d]	694	1		T68	2		T188	1		T200	2
valid_sources[0x5e]	782	1		T203	3		T143	1		T53	1
valid_sources[0x5f]	676	1		T33	1		T40	1		T223	1
valid_sources[0x60]	838	1		T224	3		T177	1		T200	2
valid_sources[0x61]	627	1		T180	1		T183	1		T61	2
valid_sources[0x62]	697	1		T207	3		T225	3		T226	1
valid_sources[0x63]	628	1		T225	7		T215	1		T64	1
valid_sources[0x64]	634	1		T61	1		T81	2		T88	2
valid_sources[0x65]	828	1		T19	1		T203	3		T227	1
valid_sources[0x66]	697	1		T2	1		T190	1		T58	1
valid_sources[0x67]	735	1		T200	1		T61	1		T62	2
valid_sources[0x68]	812	1		T167	1		T228	1		T229	2
valid_sources[0x69]	1002	1		T57	1		T58	5		T62	3
valid_sources[0x6a]	705	1		T62	2		T88	3		T59	4
valid_sources[0x6b]	579	1		T139	1		T61	1		T62	7
valid_sources[0x6c]	788	1		T200	1		T61	2		T62	4
valid_sources[0x6d]	795	1		T61	1		T58	1		T62	3
valid_sources[0x6e]	684	1		T19	1		T230	4		T231	1
valid_sources[0x6f]	871	1		T200	1		T145	2		T61	1
valid_sources[0x70]	688	1		T232	7		T61	2		T58	1
valid_sources[0x71]	704	1		T130	1		T139	1		T61	1
valid_sources[0x72]	579	1		T63	7		T61	2		T81	1
valid_sources[0x73]	621	1		T62	2		T81	1		T88	2
valid_sources[0x74]	615	1		T195	1		T28	1		T88	3
valid_sources[0x75]	793	1		T226	1		T193	1		T61	2
valid_sources[0x76]	781	1		T233	12		T43	1		T234	1
valid_sources[0x77]	736	1		T71	1		T200	1		T235	1
valid_sources[0x78]	787	1		T61	2		T58	1		T81	2
valid_sources[0x79]	624	1		T186	1		T134	1		T143	1
valid_sources[0x7a]	686	1		T45	2		T10	1		T208	9
valid_sources[0x7b]	841	1		T236	20		T61	6		T81	2
valid_sources[0x7c]	771	1		T68	1		T61	1		T88	1
valid_sources[0x7d]	1018	1		T184	1		T61	2		T88	3
valid_sources[0x7e]	717	1		T69	1		T183	1		T64	1
valid_sources[0x7f]	635	1		T61	3		T62	7		T81	3
valid_sources[0x80]	806	1		T33	1		T237	1		T61	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45303

1

T63

21

T64

2

T61

89

values[0x0]

all_enables

biggest_size

64542

1

T1

5

T2

2

T3

4

values[0x1]

all_enables

biggest_size

64755

1

T1

5

T3

1

T4

4