Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	1146939	1		T4	18		T7	8		T8	30
full_word	706139	1		T4	8		T7	6		T10	80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1852778	1		T4	26		T7	14		T10	80
auto[TlIntgErrCmd]	96	1		T58	7		T84	6		T85	8
auto[TlIntgErrData]	97	1		T58	9		T84	7		T85	5
auto[TlIntgErrBoth]	107	1		T58	4		T84	7		T85	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	560268	1		T4	8		T7	6		T10	80
auto[1]	1292810	1		T4	18		T7	8		T8	39

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	233955	1		T4	6		T7	3		T17	3
auto[TlIntgErrNone]	partial	auto[1]	912715	1		T4	12		T7	5		T8	30
auto[TlIntgErrNone]	full_word	auto[0]	326178	1		T4	2		T7	3		T10	80
auto[TlIntgErrNone]	full_word	auto[1]	379930	1		T4	6		T7	3		T8	9
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T58	5		T84	1		T85	6
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T58	1		T84	4		T85	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T85	1		T154	1		T159	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T58	1		T84	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T58	5		T84	5		T95	5
auto[TlIntgErrData]	partial	auto[1]	47	1		T58	4		T84	1		T85	4
auto[TlIntgErrData]	full_word	auto[0]	7	1		T84	1		T154	1		T160	3
auto[TlIntgErrData]	full_word	auto[1]	4	1		T85	1		T154	1		T159	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T84	3		T85	2		T95	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T58	4		T84	4		T85	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T154	1		T160	1		T157	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T95	1		T154	3		T126	3