Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 134705939 246490 0 0
late_debug_enable_rd_A 134705939 24658 0 0
late_debug_enable_regwen_rd_A 134705939 18836 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 134705939 246490 0 0
T58 130496 10 0 0
T59 456511 2591 0 0
T60 10951 5 0 0
T61 15085 742 0 0
T62 20165 427 0 0
T75 813876 104561 0 0
T81 8056 758 0 0
T83 25421 760 0 0
T84 55418 4 0 0
T85 147024 6 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 134705939 24658 0 0
T60 10951 8 0 0
T85 147024 97 0 0
T88 421529 1012 0 0
T90 40731 7 0 0
T92 8049 3 0 0
T104 5038 3 0 0
T119 41276 85 0 0
T125 318333 4126 0 0
T126 195271 51 0 0
T127 10342 4 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 134705939 18836 0 0
T60 10951 16 0 0
T85 147024 85 0 0
T90 40731 54 0 0
T92 8049 4 0 0
T107 25573 6 0 0
T119 41276 15 0 0
T125 318333 3269 0 0
T126 195271 30 0 0
T127 10342 2 0 0
T128 5202 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%