Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51834921 |
51797545 |
0 |
0 |
T1 |
223152 |
222467 |
0 |
0 |
T2 |
2071 |
2015 |
0 |
0 |
T3 |
23774 |
23485 |
0 |
0 |
T4 |
562842 |
562529 |
0 |
0 |
T7 |
7086 |
7030 |
0 |
0 |
T16 |
244432 |
244379 |
0 |
0 |
T29 |
124324 |
124264 |
0 |
0 |
T31 |
31611 |
31533 |
0 |
0 |
T44 |
155627 |
155539 |
0 |
0 |
T45 |
1273 |
1215 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51834921 |
51797545 |
0 |
0 |
T1 |
223152 |
222467 |
0 |
0 |
T2 |
2071 |
2015 |
0 |
0 |
T3 |
23774 |
23485 |
0 |
0 |
T4 |
562842 |
562529 |
0 |
0 |
T7 |
7086 |
7030 |
0 |
0 |
T16 |
244432 |
244379 |
0 |
0 |
T29 |
124324 |
124264 |
0 |
0 |
T31 |
31611 |
31533 |
0 |
0 |
T44 |
155627 |
155539 |
0 |
0 |
T45 |
1273 |
1215 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51834921 |
51797545 |
0 |
0 |
T1 |
223152 |
222467 |
0 |
0 |
T2 |
2071 |
2015 |
0 |
0 |
T3 |
23774 |
23485 |
0 |
0 |
T4 |
562842 |
562529 |
0 |
0 |
T7 |
7086 |
7030 |
0 |
0 |
T16 |
244432 |
244379 |
0 |
0 |
T29 |
124324 |
124264 |
0 |
0 |
T31 |
31611 |
31533 |
0 |
0 |
T44 |
155627 |
155539 |
0 |
0 |
T45 |
1273 |
1215 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51834921 |
51797545 |
0 |
0 |
T1 |
223152 |
222467 |
0 |
0 |
T2 |
2071 |
2015 |
0 |
0 |
T3 |
23774 |
23485 |
0 |
0 |
T4 |
562842 |
562529 |
0 |
0 |
T7 |
7086 |
7030 |
0 |
0 |
T16 |
244432 |
244379 |
0 |
0 |
T29 |
124324 |
124264 |
0 |
0 |
T31 |
31611 |
31533 |
0 |
0 |
T44 |
155627 |
155539 |
0 |
0 |
T45 |
1273 |
1215 |
0 |
0 |