Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8445062 8443742 0 0
selKnown1 57880527 57879207 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8445062 8443742 0 0
T1 53881 53877 0 0
T2 618 614 0 0
T3 16741 16737 0 0
T4 38574 38570 0 0
T7 5702 5698 0 0
T8 0 10 0 0
T16 27224 27220 0 0
T17 0 12 0 0
T29 213835 213831 0 0
T31 5311 5307 0 0
T33 0 12 0 0
T39 0 2 0 0
T44 24408 24404 0 0
T45 886 882 0 0
T48 0 20 0 0
T54 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 57880527 57879207 0 0
T1 250102 250098 0 0
T2 2381 2377 0 0
T3 32149 32145 0 0
T4 582131 582127 0 0
T7 9938 9934 0 0
T8 0 8 0 0
T16 258045 258041 0 0
T17 0 2 0 0
T29 231249 231245 0 0
T31 34267 34263 0 0
T33 0 12 0 0
T39 0 2 0 0
T44 167832 167828 0 0
T45 1717 1713 0 0
T48 0 20 0 0
T54 0 6 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2399065 2398845 0 0
selKnown1 51834921 51834701 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2399065 2398845 0 0
T1 26930 26929 0 0
T2 308 307 0 0
T3 8365 8364 0 0
T4 19279 19278 0 0
T7 2850 2849 0 0
T16 13611 13610 0 0
T29 106909 106908 0 0
T31 2654 2653 0 0
T44 12203 12202 0 0
T45 442 441 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 51834921 51834701 0 0
T1 223152 223151 0 0
T2 2071 2070 0 0
T3 23774 23773 0 0
T4 562842 562841 0 0
T7 7086 7085 0 0
T16 244432 244431 0 0
T29 124324 124323 0 0
T31 31611 31610 0 0
T44 155627 155626 0 0
T45 1273 1272 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 578 358 0 0
selKnown1 555 335 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 578 358 0 0
T1 10 9 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 5 4 0 0
T7 1 0 0 0
T8 0 5 0 0
T16 1 0 0 0
T17 0 1 0 0
T29 8 7 0 0
T31 1 0 0 0
T33 0 6 0 0
T39 0 1 0 0
T44 1 0 0 0
T45 1 0 0 0
T48 0 10 0 0
T54 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 555 335 0 0
T1 10 9 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 5 4 0 0
T7 1 0 0 0
T8 0 4 0 0
T16 1 0 0 0
T17 0 1 0 0
T29 8 7 0 0
T31 1 0 0 0
T33 0 6 0 0
T39 0 1 0 0
T44 1 0 0 0
T45 1 0 0 0
T48 0 10 0 0
T54 0 3 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6043598 6043158 0 0
selKnown1 6043393 6042953 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6043598 6043158 0 0
T1 26931 26930 0 0
T2 308 307 0 0
T3 8366 8365 0 0
T4 19279 19278 0 0
T7 2850 2849 0 0
T16 13611 13610 0 0
T29 106910 106909 0 0
T31 2655 2654 0 0
T44 12203 12202 0 0
T45 442 441 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6043393 6042953 0 0
T1 26930 26929 0 0
T2 308 307 0 0
T3 8365 8364 0 0
T4 19279 19278 0 0
T7 2850 2849 0 0
T16 13611 13610 0 0
T29 106909 106908 0 0
T31 2654 2653 0 0
T44 12203 12202 0 0
T45 442 441 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1821 1381 0 0
selKnown1 1658 1218 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1821 1381 0 0
T1 10 9 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 11 10 0 0
T7 1 0 0 0
T8 0 5 0 0
T16 1 0 0 0
T17 0 11 0 0
T29 8 7 0 0
T31 1 0 0 0
T33 0 6 0 0
T39 0 1 0 0
T44 1 0 0 0
T45 1 0 0 0
T48 0 10 0 0
T54 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1658 1218 0 0
T1 10 9 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 5 4 0 0
T7 1 0 0 0
T8 0 4 0 0
T16 1 0 0 0
T17 0 1 0 0
T29 8 7 0 0
T31 1 0 0 0
T33 0 6 0 0
T39 0 1 0 0
T44 1 0 0 0
T45 1 0 0 0
T48 0 10 0 0
T54 0 3 0 0

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