SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1320 | 1320 | 0 | 0 |
OutputsKnown_A | 311009526 | 310785270 | 0 | 0 |
gen_flops.OutputDelay_A | 155504763 | 155387640 | 0 | 1980 |
gen_no_flops.OutputDelay_A | 155504763 | 155392635 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1320 | 1320 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
T31 | 6 | 6 | 0 | 0 |
T44 | 6 | 6 | 0 | 0 |
T45 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 311009526 | 310785270 | 0 | 0 |
T1 | 1338912 | 1334802 | 0 | 0 |
T2 | 12426 | 12090 | 0 | 0 |
T3 | 142644 | 140910 | 0 | 0 |
T4 | 3377052 | 3375174 | 0 | 0 |
T7 | 42516 | 42180 | 0 | 0 |
T16 | 1466592 | 1466274 | 0 | 0 |
T29 | 745944 | 745584 | 0 | 0 |
T31 | 189666 | 189198 | 0 | 0 |
T44 | 933762 | 933234 | 0 | 0 |
T45 | 7638 | 7290 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 155504763 | 155387640 | 0 | 1980 |
T1 | 669456 | 667311 | 0 | 9 |
T2 | 6213 | 6036 | 0 | 9 |
T3 | 71322 | 70410 | 0 | 9 |
T4 | 1688526 | 1687542 | 0 | 9 |
T7 | 21258 | 21081 | 0 | 9 |
T16 | 733296 | 733128 | 0 | 9 |
T29 | 372972 | 372786 | 0 | 9 |
T31 | 94833 | 94590 | 0 | 9 |
T44 | 466881 | 466608 | 0 | 9 |
T45 | 3819 | 3636 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 155504763 | 155392635 | 0 | 0 |
T1 | 669456 | 667401 | 0 | 0 |
T2 | 6213 | 6045 | 0 | 0 |
T3 | 71322 | 70455 | 0 | 0 |
T4 | 1688526 | 1687587 | 0 | 0 |
T7 | 21258 | 21090 | 0 | 0 |
T16 | 733296 | 733137 | 0 | 0 |
T29 | 372972 | 372792 | 0 | 0 |
T31 | 94833 | 94599 | 0 | 0 |
T44 | 466881 | 466617 | 0 | 0 |
T45 | 3819 | 3645 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 220 | 220 | 0 | 0 |
OutputsKnown_A | 51834921 | 51797545 | 0 | 0 |
gen_flops.OutputDelay_A | 51834921 | 51795880 | 0 | 660 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 220 | 220 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51795880 | 0 | 660 |
T1 | 223152 | 222437 | 0 | 3 |
T2 | 2071 | 2012 | 0 | 3 |
T3 | 23774 | 23470 | 0 | 3 |
T4 | 562842 | 562514 | 0 | 3 |
T7 | 7086 | 7027 | 0 | 3 |
T16 | 244432 | 244376 | 0 | 3 |
T29 | 124324 | 124262 | 0 | 3 |
T31 | 31611 | 31530 | 0 | 3 |
T44 | 155627 | 155536 | 0 | 3 |
T45 | 1273 | 1212 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 220 | 220 | 0 | 0 |
OutputsKnown_A | 51834921 | 51797545 | 0 | 0 |
gen_flops.OutputDelay_A | 51834921 | 51795880 | 0 | 660 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 220 | 220 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51795880 | 0 | 660 |
T1 | 223152 | 222437 | 0 | 3 |
T2 | 2071 | 2012 | 0 | 3 |
T3 | 23774 | 23470 | 0 | 3 |
T4 | 562842 | 562514 | 0 | 3 |
T7 | 7086 | 7027 | 0 | 3 |
T16 | 244432 | 244376 | 0 | 3 |
T29 | 124324 | 124262 | 0 | 3 |
T31 | 31611 | 31530 | 0 | 3 |
T44 | 155627 | 155536 | 0 | 3 |
T45 | 1273 | 1212 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 220 | 220 | 0 | 0 |
OutputsKnown_A | 51834921 | 51797545 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51834921 | 51797545 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 220 | 220 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 220 | 220 | 0 | 0 |
OutputsKnown_A | 51834921 | 51797545 | 0 | 0 |
gen_flops.OutputDelay_A | 51834921 | 51795880 | 0 | 660 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 220 | 220 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51795880 | 0 | 660 |
T1 | 223152 | 222437 | 0 | 3 |
T2 | 2071 | 2012 | 0 | 3 |
T3 | 23774 | 23470 | 0 | 3 |
T4 | 562842 | 562514 | 0 | 3 |
T7 | 7086 | 7027 | 0 | 3 |
T16 | 244432 | 244376 | 0 | 3 |
T29 | 124324 | 124262 | 0 | 3 |
T31 | 31611 | 31530 | 0 | 3 |
T44 | 155627 | 155536 | 0 | 3 |
T45 | 1273 | 1212 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 220 | 220 | 0 | 0 |
OutputsKnown_A | 51834921 | 51797545 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51834921 | 51797545 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 220 | 220 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 220 | 220 | 0 | 0 |
OutputsKnown_A | 51834921 | 51797545 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51834921 | 51797545 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 220 | 220 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51834921 | 51797545 | 0 | 0 |
T1 | 223152 | 222467 | 0 | 0 |
T2 | 2071 | 2015 | 0 | 0 |
T3 | 23774 | 23485 | 0 | 0 |
T4 | 562842 | 562529 | 0 | 0 |
T7 | 7086 | 7030 | 0 | 0 |
T16 | 244432 | 244379 | 0 | 0 |
T29 | 124324 | 124264 | 0 | 0 |
T31 | 31611 | 31533 | 0 | 0 |
T44 | 155627 | 155539 | 0 | 0 |
T45 | 1273 | 1215 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |