Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 238327 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 571969 1 T8 2 T7 7 T46 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 486212 1 T7 8 T5 1 T6 12
values[0x0] 146698 1 T8 2 T4 3 T46 1
values[0x1] 177386 1 T7 1 T4 1 T5 24



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 168229 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 642067 1 T8 2 T7 7 T46 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4002 1 T5 1 T60 3 T63 19
valid_sources[0x01] 3120 1 T5 1 T15 2 T160 3
valid_sources[0x02] 3380 1 T5 1 T161 1 T162 2
valid_sources[0x03] 3060 1 T5 2 T42 4 T60 8
valid_sources[0x04] 2877 1 T41 1 T62 1 T59 3
valid_sources[0x05] 3115 1 T4 1 T5 1 T62 1
valid_sources[0x06] 2780 1 T62 2 T60 1 T63 18
valid_sources[0x07] 3194 1 T59 5 T60 14 T63 23
valid_sources[0x08] 3158 1 T163 1 T60 4 T63 20
valid_sources[0x09] 2992 1 T24 1 T62 2 T60 1
valid_sources[0x0a] 3216 1 T5 1 T135 8 T62 1
valid_sources[0x0b] 3881 1 T59 12 T60 7 T63 21
valid_sources[0x0c] 3014 1 T5 1 T63 10 T61 37
valid_sources[0x0d] 2657 1 T138 1 T62 3 T60 4
valid_sources[0x0e] 2912 1 T7 9 T40 1 T162 2
valid_sources[0x0f] 3287 1 T135 3 T60 10 T63 13
valid_sources[0x10] 3440 1 T37 4 T141 2 T62 2
valid_sources[0x11] 2856 1 T5 1 T43 1 T62 1
valid_sources[0x12] 3387 1 T124 1 T62 1 T60 1
valid_sources[0x13] 2904 1 T18 1 T163 1 T40 1
valid_sources[0x14] 2956 1 T144 1 T138 1 T62 2
valid_sources[0x15] 3390 1 T5 2 T161 1 T62 6
valid_sources[0x16] 3001 1 T22 1 T37 4 T138 1
valid_sources[0x17] 2853 1 T140 1 T42 1 T62 1
valid_sources[0x18] 2990 1 T162 2 T145 5 T62 1
valid_sources[0x19] 3105 1 T43 3 T24 2 T62 1
valid_sources[0x1a] 3010 1 T6 1 T164 2 T145 4
valid_sources[0x1b] 3201 1 T140 1 T62 1 T63 18
valid_sources[0x1c] 3553 1 T43 2 T161 1 T42 1
valid_sources[0x1d] 3581 1 T40 1 T62 1 T60 2
valid_sources[0x1e] 3054 1 T5 1 T14 3 T122 1
valid_sources[0x1f] 2727 1 T62 2 T63 25 T61 54
valid_sources[0x20] 2837 1 T39 9 T63 11 T61 34
valid_sources[0x21] 3037 1 T6 1 T43 1 T44 1
valid_sources[0x22] 3109 1 T130 1 T63 17 T61 62
valid_sources[0x23] 3085 1 T6 1 T62 1 T60 2
valid_sources[0x24] 3940 1 T144 1 T138 2 T130 1
valid_sources[0x25] 2959 1 T6 1 T62 1 T60 6
valid_sources[0x26] 2968 1 T62 1 T60 1 T63 43
valid_sources[0x27] 3037 1 T43 2 T21 4 T60 2
valid_sources[0x28] 3458 1 T122 1 T138 1 T62 1
valid_sources[0x29] 3258 1 T21 3 T144 1 T141 1
valid_sources[0x2a] 2722 1 T19 2 T62 2 T63 27
valid_sources[0x2b] 3375 1 T5 1 T43 1 T40 1
valid_sources[0x2c] 3037 1 T18 1 T29 3 T38 80
valid_sources[0x2d] 2899 1 T6 1 T43 1 T21 2
valid_sources[0x2e] 3062 1 T25 7 T62 1 T59 5
valid_sources[0x2f] 2996 1 T44 1 T59 5 T63 27
valid_sources[0x30] 2768 1 T22 1 T62 4 T60 2
valid_sources[0x31] 3419 1 T18 1 T62 1 T59 9
valid_sources[0x32] 2907 1 T138 1 T62 1 T60 1
valid_sources[0x33] 2996 1 T5 1 T165 1 T62 2
valid_sources[0x34] 3557 1 T5 1 T21 2 T161 1
valid_sources[0x35] 2992 1 T60 4 T63 15 T61 37
valid_sources[0x36] 3895 1 T43 1 T145 4 T62 2
valid_sources[0x37] 3088 1 T122 1 T130 1 T19 1
valid_sources[0x38] 3494 1 T40 1 T161 1 T62 1
valid_sources[0x39] 3191 1 T5 1 T6 1 T160 3
valid_sources[0x3a] 3736 1 T5 1 T6 1 T62 1
valid_sources[0x3b] 2900 1 T160 2 T62 1 T60 9
valid_sources[0x3c] 3567 1 T162 1 T63 25 T61 37
valid_sources[0x3d] 3131 1 T60 5 T63 30 T61 34
valid_sources[0x3e] 2954 1 T43 3 T138 1 T62 5
valid_sources[0x3f] 3162 1 T166 7 T62 2 T63 30
valid_sources[0x40] 2959 1 T5 1 T62 1 T60 1
valid_sources[0x41] 3160 1 T21 4 T144 1 T62 1
valid_sources[0x42] 2920 1 T122 1 T162 1 T62 3
valid_sources[0x43] 2953 1 T5 1 T15 2 T138 2
valid_sources[0x44] 2957 1 T62 1 T59 7 T63 18
valid_sources[0x45] 2874 1 T43 1 T138 1 T59 4
valid_sources[0x46] 2809 1 T5 1 T29 1 T43 1
valid_sources[0x47] 2802 1 T10 45 T11 1 T167 1
valid_sources[0x48] 2871 1 T62 1 T59 7 T63 17
valid_sources[0x49] 2820 1 T29 1 T41 2 T62 1
valid_sources[0x4a] 2903 1 T24 1 T124 1 T59 1
valid_sources[0x4b] 3045 1 T130 1 T62 2 T60 2
valid_sources[0x4c] 4919 1 T5 1 T18 1 T60 4
valid_sources[0x4d] 3444 1 T6 2 T60 7 T63 12
valid_sources[0x4e] 2861 1 T124 1 T62 1 T59 3
valid_sources[0x4f] 2753 1 T6 1 T62 1 T60 1
valid_sources[0x50] 3336 1 T60 5 T63 35 T61 39
valid_sources[0x51] 5084 1 T122 1 T62 4 T60 3
valid_sources[0x52] 3483 1 T6 2 T167 1 T62 2
valid_sources[0x53] 2704 1 T5 1 T6 1 T62 1
valid_sources[0x54] 3321 1 T42 1 T62 1 T60 3
valid_sources[0x55] 3386 1 T6 1 T164 4 T62 3
valid_sources[0x56] 2865 1 T62 1 T60 1 T63 15
valid_sources[0x57] 3361 1 T62 1 T59 275 T60 1
valid_sources[0x58] 3050 1 T131 56 T42 2 T62 2
valid_sources[0x59] 3354 1 T6 1 T22 2 T59 6
valid_sources[0x5a] 3863 1 T43 1 T15 5 T62 4
valid_sources[0x5b] 3274 1 T161 2 T138 2 T62 3
valid_sources[0x5c] 5016 1 T62 1 T60 1 T63 14
valid_sources[0x5d] 3247 1 T138 1 T62 1 T59 12
valid_sources[0x5e] 3104 1 T162 2 T62 1 T59 3
valid_sources[0x5f] 3398 1 T42 1 T62 1 T60 3
valid_sources[0x60] 3271 1 T167 1 T168 1 T63 24
valid_sources[0x61] 3196 1 T4 1 T46 1 T124 1
valid_sources[0x62] 3266 1 T21 2 T62 1 T63 21
valid_sources[0x63] 2609 1 T5 1 T62 2 T60 14
valid_sources[0x64] 3106 1 T6 1 T124 1 T60 11
valid_sources[0x65] 3395 1 T62 1 T63 16 T61 44
valid_sources[0x66] 2882 1 T39 3 T40 1 T41 1
valid_sources[0x67] 3083 1 T43 2 T60 9 T63 19
valid_sources[0x68] 3305 1 T6 1 T160 1 T62 2
valid_sources[0x69] 3430 1 T138 1 T62 2 T63 29
valid_sources[0x6a] 2913 1 T60 1 T63 38 T61 38
valid_sources[0x6b] 3070 1 T162 1 T59 153 T60 3
valid_sources[0x6c] 3075 1 T60 3 T63 33 T61 48
valid_sources[0x6d] 3642 1 T161 1 T138 1 T162 1
valid_sources[0x6e] 3395 1 T6 4 T18 2 T40 1
valid_sources[0x6f] 3106 1 T144 2 T62 3 T63 21
valid_sources[0x70] 2997 1 T60 1 T63 27 T61 45
valid_sources[0x71] 3571 1 T6 1 T40 1 T12 36
valid_sources[0x72] 2870 1 T62 2 T60 4 T63 10
valid_sources[0x73] 2930 1 T5 1 T11 5 T25 1
valid_sources[0x74] 2940 1 T121 46 T22 2 T122 1
valid_sources[0x75] 2929 1 T169 5 T62 1 T60 3
valid_sources[0x76] 3479 1 T5 1 T18 2 T163 2
valid_sources[0x77] 2812 1 T37 16 T135 2 T63 22
valid_sources[0x78] 3078 1 T41 1 T138 1 T60 2
valid_sources[0x79] 2999 1 T43 1 T164 5 T19 1
valid_sources[0x7a] 2845 1 T5 1 T140 1 T62 1
valid_sources[0x7b] 2861 1 T138 1 T42 1 T62 1
valid_sources[0x7c] 3198 1 T8 2 T5 1 T138 1
valid_sources[0x7d] 2800 1 T5 2 T130 2 T62 2
valid_sources[0x7e] 3051 1 T43 1 T124 1 T19 3
valid_sources[0x7f] 2975 1 T122 1 T124 1 T19 1
valid_sources[0x80] 4099 1 T22 1 T167 1 T62 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 288374 1 T7 7 T6 6 T18 1
values[0x0] all_enables biggest_size 142014 1 T8 2 T46 1 T5 7
values[0x1] all_enables biggest_size 141581 1 T5 6 T6 4 T18 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6525 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 66319 1 T1 1 T2 1 T3 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 21613 1 T62 76 T59 89 T60 35
values[0x0] 25057 1 T3 3 T16 1 T9 2
values[0x1] 26174 1 T1 1 T2 1 T3 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4513 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 68331 1 T1 1 T2 1 T3 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 409 1 T14 1 T170 1 T171 2
valid_sources[0x01] 445 1 T62 3 T60 3 T71 65
valid_sources[0x02] 287 1 T172 2 T145 1 T60 1
valid_sources[0x03] 244 1 T173 2 T71 77 T72 6
valid_sources[0x04] 175 1 T174 1 T175 1 T176 1
valid_sources[0x05] 261 1 T36 1 T176 1 T71 88
valid_sources[0x06] 171 1 T47 1 T177 1 T178 7
valid_sources[0x07] 155 1 T1 1 T179 1 T62 1
valid_sources[0x08] 249 1 T123 1 T62 5 T71 77
valid_sources[0x09] 165 1 T71 73 T78 1 T81 1
valid_sources[0x0a] 463 1 T14 1 T141 6 T71 62
valid_sources[0x0b] 181 1 T9 1 T180 2 T62 2
valid_sources[0x0c] 315 1 T181 1 T161 1 T176 1
valid_sources[0x0d] 251 1 T120 1 T182 1 T172 1
valid_sources[0x0e] 361 1 T34 1 T170 1 T61 2
valid_sources[0x0f] 148 1 T183 1 T184 1 T185 7
valid_sources[0x10] 218 1 T186 2 T187 2 T188 1
valid_sources[0x11] 330 1 T189 7 T172 1 T59 1
valid_sources[0x12] 189 1 T133 1 T190 2 T71 65
valid_sources[0x13] 149 1 T191 1 T185 1 T62 1
valid_sources[0x14] 231 1 T6 1 T68 1 T192 2
valid_sources[0x15] 126 1 T5 2 T142 1 T62 12
valid_sources[0x16] 152 1 T33 1 T193 1 T194 1
valid_sources[0x17] 152 1 T195 4 T196 2 T60 5
valid_sources[0x18] 174 1 T50 1 T197 1 T198 2
valid_sources[0x19] 518 1 T71 64 T72 6 T73 4
valid_sources[0x1a] 198 1 T11 1 T128 2 T199 1
valid_sources[0x1b] 521 1 T17 1 T4 7 T200 1
valid_sources[0x1c] 134 1 T30 1 T60 2 T71 53
valid_sources[0x1d] 343 1 T129 1 T62 3 T71 65
valid_sources[0x1e] 140 1 T196 2 T60 2 T71 59
valid_sources[0x1f] 303 1 T174 1 T142 1 T60 1
valid_sources[0x20] 250 1 T68 1 T161 2 T201 3
valid_sources[0x21] 241 1 T14 1 T202 2 T71 77
valid_sources[0x22] 174 1 T203 5 T204 1 T178 8
valid_sources[0x23] 361 1 T5 1 T205 1 T43 3
valid_sources[0x24] 269 1 T68 1 T202 1 T60 6
valid_sources[0x25] 230 1 T191 1 T206 1 T207 1
valid_sources[0x26] 552 1 T63 1 T71 77 T81 1
valid_sources[0x27] 197 1 T43 4 T21 3 T62 2
valid_sources[0x28] 339 1 T190 1 T12 5 T71 77
valid_sources[0x29] 248 1 T208 1 T173 1 T60 1
valid_sources[0x2a] 427 1 T50 1 T11 1 T62 5
valid_sources[0x2b] 311 1 T135 4 T209 7 T62 2
valid_sources[0x2c] 157 1 T145 1 T71 59 T86 2
valid_sources[0x2d] 171 1 T43 1 T210 3 T211 1
valid_sources[0x2e] 142 1 T68 1 T10 1 T190 1
valid_sources[0x2f] 355 1 T62 13 T71 69 T78 1
valid_sources[0x30] 278 1 T28 1 T71 70 T146 6
valid_sources[0x31] 290 1 T71 88 T72 4 T73 3
valid_sources[0x32] 542 1 T142 1 T62 3 T71 55
valid_sources[0x33] 234 1 T212 1 T71 65 T80 1
valid_sources[0x34] 558 1 T21 3 T213 4 T208 2
valid_sources[0x35] 215 1 T31 12 T170 2 T71 69
valid_sources[0x36] 366 1 T57 1 T14 1 T214 17
valid_sources[0x37] 234 1 T197 1 T60 2 T63 1
valid_sources[0x38] 332 1 T207 10 T71 56 T80 3
valid_sources[0x39] 367 1 T6 1 T62 2 T71 53
valid_sources[0x3a] 248 1 T15 2 T62 4 T71 69
valid_sources[0x3b] 181 1 T215 1 T197 1 T62 1
valid_sources[0x3c] 260 1 T48 1 T62 3 T71 83
valid_sources[0x3d] 153 1 T216 1 T202 1 T60 2
valid_sources[0x3e] 152 1 T217 1 T176 2 T71 59
valid_sources[0x3f] 176 1 T218 1 T204 1 T60 1
valid_sources[0x40] 297 1 T41 1 T188 1 T124 3
valid_sources[0x41] 257 1 T219 7 T220 1 T62 3
valid_sources[0x42] 385 1 T221 1 T83 1 T71 55
valid_sources[0x43] 163 1 T174 1 T70 1 T71 78
valid_sources[0x44] 176 1 T170 1 T222 1 T223 3
valid_sources[0x45] 200 1 T60 3 T63 1 T71 48
valid_sources[0x46] 474 1 T10 5 T168 1 T213 4
valid_sources[0x47] 131 1 T9 2 T224 1 T225 2
valid_sources[0x48] 269 1 T221 2 T226 1 T60 4
valid_sources[0x49] 150 1 T216 1 T63 1 T71 82
valid_sources[0x4a] 256 1 T227 1 T58 1 T200 1
valid_sources[0x4b] 158 1 T71 58 T80 1 T72 10
valid_sources[0x4c] 361 1 T228 12 T59 171 T63 2
valid_sources[0x4d] 189 1 T140 1 T188 2 T62 4
valid_sources[0x4e] 126 1 T143 1 T198 5 T71 65
valid_sources[0x4f] 120 1 T229 1 T191 2 T230 5
valid_sources[0x50] 320 1 T231 1 T232 6 T71 66
valid_sources[0x51] 361 1 T9 1 T50 1 T161 2
valid_sources[0x52] 269 1 T14 1 T11 1 T71 61
valid_sources[0x53] 193 1 T233 1 T62 15 T59 1
valid_sources[0x54] 217 1 T39 1 T83 1 T71 71
valid_sources[0x55] 318 1 T49 7 T234 14 T220 1
valid_sources[0x56] 410 1 T49 1 T71 60 T78 2
valid_sources[0x57] 133 1 T71 65 T72 4 T73 2
valid_sources[0x58] 268 1 T235 1 T179 2 T142 1
valid_sources[0x59] 190 1 T28 1 T62 3 T60 2
valid_sources[0x5a] 147 1 T170 1 T145 2 T62 3
valid_sources[0x5b] 263 1 T163 1 T26 1 T62 1
valid_sources[0x5c] 170 1 T10 2 T236 1 T142 1
valid_sources[0x5d] 352 1 T139 1 T237 1 T190 1
valid_sources[0x5e] 175 1 T186 2 T62 9 T60 4
valid_sources[0x5f] 283 1 T6 3 T238 1 T71 71
valid_sources[0x60] 352 1 T60 3 T71 66 T81 1
valid_sources[0x61] 420 1 T145 1 T61 3 T71 72
valid_sources[0x62] 394 1 T176 1 T62 2 T60 1
valid_sources[0x63] 573 1 T216 1 T121 1 T142 1
valid_sources[0x64] 186 1 T2 1 T14 1 T60 3
valid_sources[0x65] 237 1 T7 1 T239 1 T225 6
valid_sources[0x66] 181 1 T63 1 T71 70 T81 2
valid_sources[0x67] 720 1 T211 1 T61 3 T71 68
valid_sources[0x68] 573 1 T240 2 T197 1 T180 2
valid_sources[0x69] 220 1 T236 1 T15 3 T71 73
valid_sources[0x6a] 269 1 T140 1 T42 1 T61 3
valid_sources[0x6b] 353 1 T170 1 T71 73 T80 1
valid_sources[0x6c] 132 1 T200 1 T174 2 T60 4
valid_sources[0x6d] 162 1 T241 1 T120 1 T55 1
valid_sources[0x6e] 133 1 T71 68 T78 1 T81 1
valid_sources[0x6f] 476 1 T242 1 T221 2 T122 7
valid_sources[0x70] 456 1 T139 1 T240 6 T237 1
valid_sources[0x71] 238 1 T160 7 T71 75 T81 1
valid_sources[0x72] 474 1 T6 1 T220 1 T179 1
valid_sources[0x73] 295 1 T63 1 T71 68 T78 1
valid_sources[0x74] 124 1 T71 64 T78 1 T81 2
valid_sources[0x75] 310 1 T135 6 T71 67 T78 1
valid_sources[0x76] 415 1 T6 1 T11 1 T62 1
valid_sources[0x77] 363 1 T71 66 T78 1 T81 1
valid_sources[0x78] 230 1 T26 1 T62 2 T60 2
valid_sources[0x79] 277 1 T128 1 T60 1 T71 75
valid_sources[0x7a] 167 1 T231 2 T62 1 T71 71
valid_sources[0x7b] 494 1 T210 1 T63 1 T71 69
valid_sources[0x7c] 175 1 T61 3 T71 77 T78 1
valid_sources[0x7d] 153 1 T211 2 T61 3 T71 59
valid_sources[0x7e] 215 1 T198 2 T62 8 T71 69
valid_sources[0x7f] 230 1 T16 2 T174 1 T243 2
valid_sources[0x80] 190 1 T66 1 T190 5 T71 58



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 18116 1 T62 72 T59 80 T60 30
values[0x0] all_enables biggest_size 24167 1 T3 2 T16 1 T9 2
values[0x1] all_enables biggest_size 24036 1 T1 1 T2 1 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%