Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	478091	1		T7	2		T4	4		T5	32
full_word	580472	1		T8	2		T7	7		T5	13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1058263	1		T8	2		T7	9		T4	4
auto[TlIntgErrCmd]	99	1		T61	11		T118	7		T119	2
auto[TlIntgErrData]	94	1		T61	6		T118	7		T119	2
auto[TlIntgErrBoth]	107	1		T61	3		T118	6		T119	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	496391	1		T7	8		T5	1		T6	12
auto[1]	562172	1		T8	2		T7	1		T4	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	206853	1		T7	1		T5	1		T6	6
auto[TlIntgErrNone]	partial	auto[1]	270966	1		T7	1		T4	4		T5	31
auto[TlIntgErrNone]	full_word	auto[0]	289399	1		T7	7		T6	6		T18	1
auto[TlIntgErrNone]	full_word	auto[1]	291045	1		T8	2		T5	13		T6	9
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T61	5		T118	2		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T61	6		T118	4		T119	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T150	1		T153	1		T148	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T118	1		T116	2		T154	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T61	3		T118	1		T119	1
auto[TlIntgErrData]	partial	auto[1]	39	1		T61	1		T118	3		T119	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T61	1		T118	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T61	1		T118	2		T155	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1		T61	1		T118	3		T119	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T61	2		T118	3		T119	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T147	1		T153	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T119	1		T157	1		T158	1