Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	158363891	71751	0	0
late_debug_enable_rd_A	158363891	3993	0	0
late_debug_enable_regwen_rd_A	158363891	2172	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158363891	71751	0	0
T59	5804	111	0	0
T60	29753	46	0	0
T61	112811	8	0	0
T62	10074	325	0	0
T71	181509	23144	0	0
T78	190178	26	0	0
T79	219702	54	0	0
T80	5537	32	0	0
T81	183233	45	0	0
T82	5656	220	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158363891	3993	0	0
T61	112811	63	0	0
T63	59231	14	0	0
T99	24259	6	0	0
T101	38888	89	0	0
T103	37363	27	0	0
T109	246903	196	0	0
T114	491957	475	0	0
T115	9525	122	0	0
T116	200801	73	0	0
T117	18421	123	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158363891	2172	0	0
T61	112811	44	0	0
T63	59231	52	0	0
T99	24259	34	0	0
T101	38888	67	0	0
T103	37363	5	0	0
T109	246903	254	0	0
T114	491957	458	0	0
T115	9525	109	0	0
T116	200801	95	0	0
T117	18421	123	0	0