Module Definition
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Module : prim_sparse_fsm_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_lc_gate_sba.u_state_regs 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_state_regs 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_sba.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.13 86.27 72.22 57.14 75.00 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
82.66 98.04 77.78 100.00 87.50 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00

Line Coverage for Module : prim_sparse_fsm_flop
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Module : prim_sparse_fsm_flop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 436 436 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436 436 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T45 2 2 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 218 218 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218 218 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T45 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 218 218 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218 218 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T45 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%