Module Definition
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Module : prim_alert_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 83.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alert_tx[0].u_prim_alert_sender 83.33 83.33



Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 10 83.33
Total Bits 24 20 83.33
Total Bits 0->1 12 10 83.33
Total Bits 1->0 12 10 83.33

Ports 12 10 83.33
Port Bits 24 20 83.33
Port Bits 0->1 12 10 83.33
Port Bits 1->0 12 10 83.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T16,T9,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T3,T49,T50 Yes T3,T49,T50 INPUT
alert_req_i Yes Yes T51,T52,T53 Yes T51,T52,T53 INPUT
alert_ack_o Yes Yes T51,T52,T53 Yes T51,T52,T53 OUTPUT
alert_state_o Yes Yes T51,T52,T53 Yes T51,T52,T53 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T3,T51,T52 Yes T3,T51,T52 INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T3,T51,T52 Yes T3,T51,T52 OUTPUT

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