Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45772267 |
45733931 |
0 |
0 |
T1 |
20541 |
20483 |
0 |
0 |
T2 |
258100 |
258036 |
0 |
0 |
T3 |
1753 |
1680 |
0 |
0 |
T4 |
248495 |
248212 |
0 |
0 |
T7 |
34620 |
34542 |
0 |
0 |
T8 |
14261 |
14189 |
0 |
0 |
T9 |
764079 |
763793 |
0 |
0 |
T16 |
92354 |
92103 |
0 |
0 |
T17 |
148968 |
148905 |
0 |
0 |
T45 |
297441 |
297387 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45772267 |
45733931 |
0 |
0 |
T1 |
20541 |
20483 |
0 |
0 |
T2 |
258100 |
258036 |
0 |
0 |
T3 |
1753 |
1680 |
0 |
0 |
T4 |
248495 |
248212 |
0 |
0 |
T7 |
34620 |
34542 |
0 |
0 |
T8 |
14261 |
14189 |
0 |
0 |
T9 |
764079 |
763793 |
0 |
0 |
T16 |
92354 |
92103 |
0 |
0 |
T17 |
148968 |
148905 |
0 |
0 |
T45 |
297441 |
297387 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45772267 |
45733931 |
0 |
0 |
T1 |
20541 |
20483 |
0 |
0 |
T2 |
258100 |
258036 |
0 |
0 |
T3 |
1753 |
1680 |
0 |
0 |
T4 |
248495 |
248212 |
0 |
0 |
T7 |
34620 |
34542 |
0 |
0 |
T8 |
14261 |
14189 |
0 |
0 |
T9 |
764079 |
763793 |
0 |
0 |
T16 |
92354 |
92103 |
0 |
0 |
T17 |
148968 |
148905 |
0 |
0 |
T45 |
297441 |
297387 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45772267 |
45733931 |
0 |
0 |
T1 |
20541 |
20483 |
0 |
0 |
T2 |
258100 |
258036 |
0 |
0 |
T3 |
1753 |
1680 |
0 |
0 |
T4 |
248495 |
248212 |
0 |
0 |
T7 |
34620 |
34542 |
0 |
0 |
T8 |
14261 |
14189 |
0 |
0 |
T9 |
764079 |
763793 |
0 |
0 |
T16 |
92354 |
92103 |
0 |
0 |
T17 |
148968 |
148905 |
0 |
0 |
T45 |
297441 |
297387 |
0 |
0 |