Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9430539 |
9429227 |
0 |
0 |
selKnown1 |
52665872 |
52664560 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9430539 |
9429227 |
0 |
0 |
T1 |
1004 |
1002 |
0 |
0 |
T2 |
26321 |
26319 |
0 |
0 |
T3 |
749 |
747 |
0 |
0 |
T4 |
20709 |
20705 |
0 |
0 |
T5 |
20 |
18 |
0 |
0 |
T6 |
0 |
13 |
0 |
0 |
T7 |
2714 |
2710 |
0 |
0 |
T8 |
724 |
722 |
0 |
0 |
T9 |
37249 |
37245 |
0 |
0 |
T16 |
17025 |
17021 |
0 |
0 |
T17 |
26390 |
26386 |
0 |
0 |
T18 |
0 |
15 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T33 |
2 |
0 |
0 |
0 |
T45 |
17845 |
17841 |
0 |
0 |
T46 |
2 |
0 |
0 |
0 |
T47 |
2 |
0 |
0 |
0 |
T51 |
0 |
20 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
52665872 |
52664560 |
0 |
0 |
T1 |
21043 |
21041 |
0 |
0 |
T2 |
271260 |
271258 |
0 |
0 |
T3 |
2127 |
2125 |
0 |
0 |
T4 |
258852 |
258848 |
0 |
0 |
T5 |
10 |
8 |
0 |
0 |
T6 |
0 |
8 |
0 |
0 |
T7 |
35978 |
35974 |
0 |
0 |
T8 |
14623 |
14621 |
0 |
0 |
T9 |
782707 |
782703 |
0 |
0 |
T16 |
100870 |
100866 |
0 |
0 |
T17 |
162164 |
162160 |
0 |
0 |
T18 |
0 |
6 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T33 |
2 |
0 |
0 |
0 |
T45 |
306364 |
306360 |
0 |
0 |
T46 |
2 |
0 |
0 |
0 |
T47 |
2 |
0 |
0 |
0 |
T51 |
0 |
20 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2536510 |
2536292 |
0 |
0 |
selKnown1 |
45772267 |
45772049 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2536510 |
2536292 |
0 |
0 |
T1 |
502 |
501 |
0 |
0 |
T2 |
13160 |
13159 |
0 |
0 |
T3 |
374 |
373 |
0 |
0 |
T4 |
10349 |
10348 |
0 |
0 |
T7 |
1356 |
1355 |
0 |
0 |
T8 |
362 |
361 |
0 |
0 |
T9 |
18618 |
18617 |
0 |
0 |
T16 |
8508 |
8507 |
0 |
0 |
T17 |
13194 |
13193 |
0 |
0 |
T45 |
8921 |
8920 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45772267 |
45772049 |
0 |
0 |
T1 |
20541 |
20540 |
0 |
0 |
T2 |
258100 |
258099 |
0 |
0 |
T3 |
1753 |
1752 |
0 |
0 |
T4 |
248495 |
248494 |
0 |
0 |
T7 |
34620 |
34619 |
0 |
0 |
T8 |
14261 |
14260 |
0 |
0 |
T9 |
764079 |
764078 |
0 |
0 |
T16 |
92354 |
92353 |
0 |
0 |
T17 |
148968 |
148967 |
0 |
0 |
T45 |
297441 |
297440 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596 |
378 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T9 |
5 |
4 |
0 |
0 |
T16 |
4 |
3 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T51 |
0 |
10 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579 |
361 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T9 |
5 |
4 |
0 |
0 |
T16 |
4 |
3 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T51 |
0 |
10 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6891478 |
6891040 |
0 |
0 |
selKnown1 |
6891277 |
6890839 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6891478 |
6891040 |
0 |
0 |
T1 |
502 |
501 |
0 |
0 |
T2 |
13161 |
13160 |
0 |
0 |
T3 |
375 |
374 |
0 |
0 |
T4 |
10349 |
10348 |
0 |
0 |
T7 |
1356 |
1355 |
0 |
0 |
T8 |
362 |
361 |
0 |
0 |
T9 |
18619 |
18618 |
0 |
0 |
T16 |
8509 |
8508 |
0 |
0 |
T17 |
13194 |
13193 |
0 |
0 |
T45 |
8922 |
8921 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6891277 |
6890839 |
0 |
0 |
T1 |
502 |
501 |
0 |
0 |
T2 |
13160 |
13159 |
0 |
0 |
T3 |
374 |
373 |
0 |
0 |
T4 |
10349 |
10348 |
0 |
0 |
T7 |
1356 |
1355 |
0 |
0 |
T8 |
362 |
361 |
0 |
0 |
T9 |
18618 |
18617 |
0 |
0 |
T16 |
8508 |
8507 |
0 |
0 |
T17 |
13194 |
13193 |
0 |
0 |
T45 |
8921 |
8920 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1955 |
1517 |
0 |
0 |
selKnown1 |
1749 |
1311 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1955 |
1517 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
15 |
14 |
0 |
0 |
T6 |
0 |
9 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T16 |
4 |
3 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
0 |
11 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T51 |
0 |
10 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1749 |
1311 |
0 |
0 |
T4 |
4 |
3 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T9 |
5 |
4 |
0 |
0 |
T16 |
4 |
3 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T51 |
0 |
10 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |