SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 45772267 | 45733931 | 0 | 0 |
gen_no_flops.OutputDelay_A | 45772267 | 45733931 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45772267 | 45733931 | 0 | 0 |
T1 | 20541 | 20483 | 0 | 0 |
T2 | 258100 | 258036 | 0 | 0 |
T3 | 1753 | 1680 | 0 | 0 |
T4 | 248495 | 248212 | 0 | 0 |
T7 | 34620 | 34542 | 0 | 0 |
T8 | 14261 | 14189 | 0 | 0 |
T9 | 764079 | 763793 | 0 | 0 |
T16 | 92354 | 92103 | 0 | 0 |
T17 | 148968 | 148905 | 0 | 0 |
T45 | 297441 | 297387 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 45772267 | 45733931 | 0 | 0 |
T1 | 20541 | 20483 | 0 | 0 |
T2 | 258100 | 258036 | 0 | 0 |
T3 | 1753 | 1680 | 0 | 0 |
T4 | 248495 | 248212 | 0 | 0 |
T7 | 34620 | 34542 | 0 | 0 |
T8 | 14261 | 14189 | 0 | 0 |
T9 | 764079 | 763793 | 0 | 0 |
T16 | 92354 | 92103 | 0 | 0 |
T17 | 148968 | 148905 | 0 | 0 |
T45 | 297441 | 297387 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |