SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
83.19 | 95.77 | 81.52 | 89.91 | 75.00 | 86.50 | 98.53 | 55.12 |
T96 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1510453142 | Jul 21 05:49:32 PM PDT 24 | Jul 21 05:49:59 PM PDT 24 | 4673560276 ps | ||
T297 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3688221532 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:36 PM PDT 24 | 3792754203 ps | ||
T298 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.760027838 | Jul 21 05:49:19 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 2673396462 ps | ||
T76 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2855777668 | Jul 21 05:49:12 PM PDT 24 | Jul 21 05:51:17 PM PDT 24 | 49147357716 ps | ||
T299 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.891745462 | Jul 21 05:49:23 PM PDT 24 | Jul 21 05:49:25 PM PDT 24 | 184627083 ps | ||
T300 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.293455872 | Jul 21 05:48:59 PM PDT 24 | Jul 21 05:49:01 PM PDT 24 | 715309281 ps | ||
T301 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2848600198 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:18 PM PDT 24 | 116798786 ps | ||
T92 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2554327643 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:38 PM PDT 24 | 163883567 ps | ||
T93 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4287667067 | Jul 21 05:49:29 PM PDT 24 | Jul 21 05:49:36 PM PDT 24 | 616392485 ps | ||
T302 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1176569943 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:19 PM PDT 24 | 684657850 ps | ||
T242 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3705713533 | Jul 21 05:49:44 PM PDT 24 | Jul 21 05:49:48 PM PDT 24 | 93170939 ps | ||
T94 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3818104252 | Jul 21 05:49:34 PM PDT 24 | Jul 21 05:49:37 PM PDT 24 | 107321836 ps | ||
T303 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1913088939 | Jul 21 05:49:05 PM PDT 24 | Jul 21 05:49:07 PM PDT 24 | 78573824 ps | ||
T153 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.666856044 | Jul 21 05:49:08 PM PDT 24 | Jul 21 05:49:13 PM PDT 24 | 118200744 ps | ||
T155 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2398407669 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:49:52 PM PDT 24 | 4576737208 ps | ||
T304 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.733588388 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:32 PM PDT 24 | 444173486 ps | ||
T98 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1673440561 | Jul 21 05:49:04 PM PDT 24 | Jul 21 05:49:10 PM PDT 24 | 7481493312 ps | ||
T305 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2987126009 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:19 PM PDT 24 | 332072511 ps | ||
T124 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.5631669 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:49 PM PDT 24 | 6884816683 ps | ||
T77 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4183114494 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:56:15 PM PDT 24 | 62666728907 ps | ||
T125 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1854610082 | Jul 21 05:49:46 PM PDT 24 | Jul 21 05:49:51 PM PDT 24 | 970687845 ps | ||
T306 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4105233193 | Jul 21 05:49:07 PM PDT 24 | Jul 21 05:49:09 PM PDT 24 | 372531657 ps | ||
T307 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4154549493 | Jul 21 05:49:10 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 5989013999 ps | ||
T102 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4154925691 | Jul 21 05:49:10 PM PDT 24 | Jul 21 05:50:33 PM PDT 24 | 16250251073 ps | ||
T308 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.487968566 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:19 PM PDT 24 | 2329043667 ps | ||
T309 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3836754115 | Jul 21 05:49:34 PM PDT 24 | Jul 21 05:49:35 PM PDT 24 | 422680931 ps | ||
T310 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.181408086 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:37 PM PDT 24 | 81816895 ps | ||
T311 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3121632609 | Jul 21 05:49:39 PM PDT 24 | Jul 21 05:49:40 PM PDT 24 | 39695053 ps | ||
T103 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.345150132 | Jul 21 05:49:25 PM PDT 24 | Jul 21 05:49:27 PM PDT 24 | 109368047 ps | ||
T164 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3853290685 | Jul 21 05:49:26 PM PDT 24 | Jul 21 05:49:48 PM PDT 24 | 22919237141 ps | ||
T312 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.599696958 | Jul 21 05:49:20 PM PDT 24 | Jul 21 05:49:24 PM PDT 24 | 956277368 ps | ||
T313 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2426524072 | Jul 21 05:49:07 PM PDT 24 | Jul 21 05:49:08 PM PDT 24 | 170303064 ps | ||
T314 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.262905237 | Jul 21 05:49:54 PM PDT 24 | Jul 21 05:50:00 PM PDT 24 | 112281979 ps | ||
T99 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2346412971 | Jul 21 05:49:05 PM PDT 24 | Jul 21 05:49:08 PM PDT 24 | 2089757757 ps | ||
T315 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.307175572 | Jul 21 05:49:40 PM PDT 24 | Jul 21 05:49:42 PM PDT 24 | 123089977 ps | ||
T316 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.556336122 | Jul 21 05:49:06 PM PDT 24 | Jul 21 05:51:00 PM PDT 24 | 83596361439 ps | ||
T104 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1849929618 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:34 PM PDT 24 | 101546740 ps | ||
T317 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1495171359 | Jul 21 05:49:18 PM PDT 24 | Jul 21 05:49:19 PM PDT 24 | 130997125 ps | ||
T109 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3623452969 | Jul 21 05:49:13 PM PDT 24 | Jul 21 05:49:15 PM PDT 24 | 99892843 ps | ||
T105 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.674674149 | Jul 21 05:49:46 PM PDT 24 | Jul 21 05:49:48 PM PDT 24 | 231714317 ps | ||
T318 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2353100213 | Jul 21 05:49:45 PM PDT 24 | Jul 21 05:49:49 PM PDT 24 | 904129045 ps | ||
T110 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.480502983 | Jul 21 05:49:32 PM PDT 24 | Jul 21 05:53:44 PM PDT 24 | 181162619548 ps | ||
T126 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2349262268 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:50:49 PM PDT 24 | 49869312105 ps | ||
T127 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2741426456 | Jul 21 05:49:45 PM PDT 24 | Jul 21 05:50:08 PM PDT 24 | 3554508824 ps | ||
T319 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3542614527 | Jul 21 05:49:38 PM PDT 24 | Jul 21 05:49:40 PM PDT 24 | 120757536 ps | ||
T320 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.678743500 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:33 PM PDT 24 | 860811976 ps | ||
T114 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2046671743 | Jul 21 05:49:05 PM PDT 24 | Jul 21 05:49:07 PM PDT 24 | 113359671 ps | ||
T321 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2027377024 | Jul 21 05:49:40 PM PDT 24 | Jul 21 05:49:43 PM PDT 24 | 201736655 ps | ||
T322 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3122269985 | Jul 21 05:49:10 PM PDT 24 | Jul 21 05:49:11 PM PDT 24 | 307388577 ps | ||
T323 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2949875209 | Jul 21 05:49:15 PM PDT 24 | Jul 21 05:49:16 PM PDT 24 | 173064932 ps | ||
T115 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.949294763 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:20 PM PDT 24 | 475240199 ps | ||
T324 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.247636315 | Jul 21 05:49:46 PM PDT 24 | Jul 21 05:50:00 PM PDT 24 | 4591329218 ps | ||
T154 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.515683668 | Jul 21 05:49:05 PM PDT 24 | Jul 21 05:49:15 PM PDT 24 | 2267879018 ps | ||
T325 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.906246963 | Jul 21 05:49:35 PM PDT 24 | Jul 21 05:49:38 PM PDT 24 | 120091449 ps | ||
T326 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2902097792 | Jul 21 05:49:14 PM PDT 24 | Jul 21 05:49:17 PM PDT 24 | 472320208 ps | ||
T106 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1190121714 | Jul 21 05:49:10 PM PDT 24 | Jul 21 05:49:15 PM PDT 24 | 578869345 ps | ||
T157 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.599535569 | Jul 21 05:49:54 PM PDT 24 | Jul 21 05:50:12 PM PDT 24 | 2657523007 ps | ||
T327 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3776881174 | Jul 21 05:49:37 PM PDT 24 | Jul 21 05:49:42 PM PDT 24 | 2812725561 ps | ||
T163 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2917923659 | Jul 21 05:49:16 PM PDT 24 | Jul 21 05:49:37 PM PDT 24 | 1748437111 ps | ||
T328 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.308296740 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:33 PM PDT 24 | 60999636 ps | ||
T329 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.871031351 | Jul 21 05:49:15 PM PDT 24 | Jul 21 05:49:30 PM PDT 24 | 27178814072 ps | ||
T160 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2235223882 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:57 PM PDT 24 | 5440959933 ps | ||
T118 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1379925300 | Jul 21 05:49:38 PM PDT 24 | Jul 21 05:49:46 PM PDT 24 | 421547850 ps | ||
T116 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.409168305 | Jul 21 05:49:13 PM PDT 24 | Jul 21 05:49:16 PM PDT 24 | 367624987 ps | ||
T161 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.299778556 | Jul 21 05:49:55 PM PDT 24 | Jul 21 05:50:16 PM PDT 24 | 1398065839 ps | ||
T117 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1919888213 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:50:48 PM PDT 24 | 15121124508 ps | ||
T330 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3374880372 | Jul 21 05:49:11 PM PDT 24 | Jul 21 05:50:30 PM PDT 24 | 33185246448 ps | ||
T331 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1795426349 | Jul 21 05:49:43 PM PDT 24 | Jul 21 05:49:45 PM PDT 24 | 166380076 ps | ||
T332 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1372380564 | Jul 21 05:49:06 PM PDT 24 | Jul 21 05:49:41 PM PDT 24 | 19560837187 ps | ||
T333 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.37380839 | Jul 21 05:49:15 PM PDT 24 | Jul 21 05:49:21 PM PDT 24 | 1796957219 ps | ||
T334 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2283687103 | Jul 21 05:49:09 PM PDT 24 | Jul 21 05:52:10 PM PDT 24 | 41993908569 ps | ||
T335 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2836040242 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 4392746900 ps | ||
T336 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2180902402 | Jul 21 05:49:35 PM PDT 24 | Jul 21 05:49:39 PM PDT 24 | 133932696 ps | ||
T337 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3053697503 | Jul 21 05:48:58 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 2224580099 ps | ||
T107 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3711434894 | Jul 21 05:49:18 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 2376046316 ps | ||
T338 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3248930403 | Jul 21 05:49:09 PM PDT 24 | Jul 21 05:49:13 PM PDT 24 | 2477749334 ps | ||
T156 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2605850750 | Jul 21 05:49:39 PM PDT 24 | Jul 21 05:49:50 PM PDT 24 | 2766013149 ps | ||
T339 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.24431494 | Jul 21 05:49:21 PM PDT 24 | Jul 21 05:49:23 PM PDT 24 | 360599997 ps | ||
T119 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.468039952 | Jul 21 05:49:43 PM PDT 24 | Jul 21 05:49:47 PM PDT 24 | 403836447 ps | ||
T340 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.36251384 | Jul 21 05:49:12 PM PDT 24 | Jul 21 05:50:21 PM PDT 24 | 6459025680 ps | ||
T341 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3148813866 | Jul 21 05:49:11 PM PDT 24 | Jul 21 05:49:12 PM PDT 24 | 434713455 ps | ||
T342 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2263568666 | Jul 21 05:49:25 PM PDT 24 | Jul 21 05:49:28 PM PDT 24 | 312075524 ps | ||
T343 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3527728140 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:49:43 PM PDT 24 | 218375003 ps | ||
T120 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1145954937 | Jul 21 05:49:44 PM PDT 24 | Jul 21 05:49:51 PM PDT 24 | 747335757 ps | ||
T344 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1163991451 | Jul 21 05:49:01 PM PDT 24 | Jul 21 05:49:03 PM PDT 24 | 423602233 ps | ||
T345 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1801091046 | Jul 21 05:49:45 PM PDT 24 | Jul 21 05:49:55 PM PDT 24 | 4035210034 ps | ||
T346 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3431118995 | Jul 21 05:49:21 PM PDT 24 | Jul 21 05:49:31 PM PDT 24 | 6565739102 ps | ||
T347 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.81523140 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:40 PM PDT 24 | 1470381802 ps | ||
T348 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1432865106 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:46 PM PDT 24 | 9177691986 ps | ||
T349 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2865556143 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:51:14 PM PDT 24 | 35252143749 ps | ||
T100 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2891981166 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:29 PM PDT 24 | 15960569783 ps | ||
T112 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.332786926 | Jul 21 05:49:36 PM PDT 24 | Jul 21 05:49:39 PM PDT 24 | 127149393 ps | ||
T108 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3100704519 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:38 PM PDT 24 | 4165975041 ps | ||
T350 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2732525641 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:24 PM PDT 24 | 1785415114 ps | ||
T351 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1721725240 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:49:49 PM PDT 24 | 2569500154 ps | ||
T352 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4272408191 | Jul 21 05:49:05 PM PDT 24 | Jul 21 05:49:08 PM PDT 24 | 2028942402 ps | ||
T158 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2173066649 | Jul 21 05:49:35 PM PDT 24 | Jul 21 05:49:58 PM PDT 24 | 8455188162 ps | ||
T353 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1884324893 | Jul 21 05:49:29 PM PDT 24 | Jul 21 05:49:32 PM PDT 24 | 503025129 ps | ||
T354 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1563922459 | Jul 21 05:49:16 PM PDT 24 | Jul 21 05:52:13 PM PDT 24 | 46075421995 ps | ||
T355 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2139206948 | Jul 21 05:49:55 PM PDT 24 | Jul 21 05:50:03 PM PDT 24 | 1120598921 ps | ||
T356 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2755138699 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:49:44 PM PDT 24 | 287553775 ps | ||
T357 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2450362229 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:35 PM PDT 24 | 160280615 ps | ||
T358 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1910800142 | Jul 21 05:49:07 PM PDT 24 | Jul 21 05:49:47 PM PDT 24 | 6548685073 ps | ||
T359 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3129404881 | Jul 21 05:49:06 PM PDT 24 | Jul 21 05:49:08 PM PDT 24 | 351860970 ps | ||
T360 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3974147274 | Jul 21 05:49:24 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 1281387489 ps | ||
T361 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.196550859 | Jul 21 05:49:05 PM PDT 24 | Jul 21 05:53:44 PM PDT 24 | 41062047812 ps | ||
T362 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3004850750 | Jul 21 05:49:35 PM PDT 24 | Jul 21 05:49:40 PM PDT 24 | 2400897838 ps | ||
T363 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2560684659 | Jul 21 05:49:21 PM PDT 24 | Jul 21 05:49:23 PM PDT 24 | 265169387 ps | ||
T364 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.880472716 | Jul 21 05:49:18 PM PDT 24 | Jul 21 05:50:01 PM PDT 24 | 16486583149 ps | ||
T365 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2532225599 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:21 PM PDT 24 | 400222016 ps | ||
T366 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2516231747 | Jul 21 05:49:20 PM PDT 24 | Jul 21 05:50:33 PM PDT 24 | 3375402180 ps | ||
T367 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3270942193 | Jul 21 05:49:23 PM PDT 24 | Jul 21 05:49:30 PM PDT 24 | 932094601 ps | ||
T368 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.645805373 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:49:44 PM PDT 24 | 424097032 ps | ||
T162 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1628446635 | Jul 21 05:49:48 PM PDT 24 | Jul 21 05:50:06 PM PDT 24 | 1142097000 ps | ||
T369 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3765402907 | Jul 21 05:49:07 PM PDT 24 | Jul 21 05:49:09 PM PDT 24 | 77465036 ps | ||
T370 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1341243799 | Jul 21 05:49:28 PM PDT 24 | Jul 21 05:49:34 PM PDT 24 | 2125624244 ps | ||
T371 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3670233896 | Jul 21 05:49:15 PM PDT 24 | Jul 21 05:49:45 PM PDT 24 | 12132308463 ps | ||
T372 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1525965830 | Jul 21 05:49:47 PM PDT 24 | Jul 21 05:50:12 PM PDT 24 | 32407309803 ps | ||
T101 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1199271007 | Jul 21 05:49:10 PM PDT 24 | Jul 21 05:49:17 PM PDT 24 | 2240616497 ps | ||
T373 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1541602855 | Jul 21 05:49:54 PM PDT 24 | Jul 21 05:50:01 PM PDT 24 | 1724927119 ps | ||
T374 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1759434269 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:49:50 PM PDT 24 | 1701390009 ps | ||
T375 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3793189522 | Jul 21 05:49:34 PM PDT 24 | Jul 21 05:50:32 PM PDT 24 | 19654407895 ps | ||
T376 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1376886180 | Jul 21 05:49:22 PM PDT 24 | Jul 21 05:49:26 PM PDT 24 | 83203419 ps | ||
T377 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3279137854 | Jul 21 05:49:22 PM PDT 24 | Jul 21 05:49:28 PM PDT 24 | 6426587474 ps | ||
T378 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.744693119 | Jul 21 05:49:32 PM PDT 24 | Jul 21 05:50:23 PM PDT 24 | 28932123696 ps | ||
T379 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1776930702 | Jul 21 05:49:37 PM PDT 24 | Jul 21 05:49:41 PM PDT 24 | 1875508605 ps | ||
T380 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2541332696 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:49:43 PM PDT 24 | 92350349 ps | ||
T381 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.957343694 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:49:45 PM PDT 24 | 195127544 ps | ||
T382 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3267165257 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:40 PM PDT 24 | 2144960217 ps | ||
T383 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1413340420 | Jul 21 05:49:45 PM PDT 24 | Jul 21 05:49:48 PM PDT 24 | 896049156 ps | ||
T384 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2888847493 | Jul 21 05:49:10 PM PDT 24 | Jul 21 05:49:21 PM PDT 24 | 2227883614 ps | ||
T385 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1382977005 | Jul 21 05:49:08 PM PDT 24 | Jul 21 05:49:43 PM PDT 24 | 34665375823 ps | ||
T386 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3430146122 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:36 PM PDT 24 | 114363806 ps | ||
T387 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1301923553 | Jul 21 05:49:26 PM PDT 24 | Jul 21 05:49:27 PM PDT 24 | 260310609 ps | ||
T388 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2673740013 | Jul 21 05:49:40 PM PDT 24 | Jul 21 05:49:45 PM PDT 24 | 2072285747 ps | ||
T389 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1918556552 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:21 PM PDT 24 | 1424968285 ps | ||
T390 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1500269033 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:18 PM PDT 24 | 40286839 ps | ||
T391 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2388261846 | Jul 21 05:49:25 PM PDT 24 | Jul 21 05:49:34 PM PDT 24 | 5628050259 ps | ||
T392 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2300986896 | Jul 21 05:49:46 PM PDT 24 | Jul 21 05:49:51 PM PDT 24 | 402600347 ps | ||
T393 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1671337440 | Jul 21 05:49:06 PM PDT 24 | Jul 21 05:50:02 PM PDT 24 | 61667841537 ps | ||
T394 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1427650991 | Jul 21 05:49:19 PM PDT 24 | Jul 21 05:49:23 PM PDT 24 | 221595246 ps | ||
T159 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.145941142 | Jul 21 05:49:35 PM PDT 24 | Jul 21 05:49:56 PM PDT 24 | 2292586887 ps | ||
T395 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.803404237 | Jul 21 05:49:11 PM PDT 24 | Jul 21 05:49:13 PM PDT 24 | 1618265900 ps | ||
T396 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.311778530 | Jul 21 05:49:25 PM PDT 24 | Jul 21 05:49:32 PM PDT 24 | 837166079 ps | ||
T397 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.395797251 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:50:04 PM PDT 24 | 18649877649 ps | ||
T398 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.413089219 | Jul 21 05:49:12 PM PDT 24 | Jul 21 05:49:13 PM PDT 24 | 47600937 ps | ||
T399 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2682895102 | Jul 21 05:49:15 PM PDT 24 | Jul 21 05:51:40 PM PDT 24 | 52698691260 ps | ||
T400 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2335897373 | Jul 21 05:49:07 PM PDT 24 | Jul 21 05:49:19 PM PDT 24 | 14094489738 ps | ||
T401 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2493907010 | Jul 21 05:49:12 PM PDT 24 | Jul 21 05:51:15 PM PDT 24 | 84230543733 ps | ||
T402 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.50923271 | Jul 21 05:49:45 PM PDT 24 | Jul 21 05:49:48 PM PDT 24 | 908159655 ps | ||
T403 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3171230751 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:46 PM PDT 24 | 1566198775 ps | ||
T404 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.476317363 | Jul 21 05:49:34 PM PDT 24 | Jul 21 05:49:52 PM PDT 24 | 5798990663 ps | ||
T405 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.36526867 | Jul 21 05:49:23 PM PDT 24 | Jul 21 05:49:24 PM PDT 24 | 109521659 ps | ||
T406 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2842749070 | Jul 21 05:49:19 PM PDT 24 | Jul 21 05:49:21 PM PDT 24 | 1073027237 ps | ||
T407 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.292472245 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:32 PM PDT 24 | 283095607 ps | ||
T408 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2862761108 | Jul 21 05:49:54 PM PDT 24 | Jul 21 05:49:56 PM PDT 24 | 167096239 ps | ||
T409 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3620643794 | Jul 21 05:49:22 PM PDT 24 | Jul 21 05:49:46 PM PDT 24 | 4463953373 ps | ||
T410 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2152591521 | Jul 21 05:49:24 PM PDT 24 | Jul 21 05:49:49 PM PDT 24 | 6806701127 ps | ||
T411 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1248255181 | Jul 21 05:49:22 PM PDT 24 | Jul 21 05:49:25 PM PDT 24 | 57019828 ps | ||
T412 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.638762519 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:49:48 PM PDT 24 | 403285513 ps | ||
T413 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2798793132 | Jul 21 05:49:02 PM PDT 24 | Jul 21 05:49:04 PM PDT 24 | 172429959 ps | ||
T414 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.641902309 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:34 PM PDT 24 | 185676207 ps | ||
T415 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3300659918 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:50:11 PM PDT 24 | 72889454968 ps | ||
T111 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.492613790 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:49:44 PM PDT 24 | 188831486 ps | ||
T416 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.676252204 | Jul 21 05:49:25 PM PDT 24 | Jul 21 05:49:30 PM PDT 24 | 276371122 ps | ||
T417 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3685909415 | Jul 21 05:49:26 PM PDT 24 | Jul 21 05:49:29 PM PDT 24 | 187306182 ps | ||
T418 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1617445481 | Jul 21 05:49:35 PM PDT 24 | Jul 21 05:49:37 PM PDT 24 | 679740880 ps | ||
T419 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1755058450 | Jul 21 05:49:41 PM PDT 24 | Jul 21 05:49:42 PM PDT 24 | 188257980 ps | ||
T420 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2924667297 | Jul 21 05:49:39 PM PDT 24 | Jul 21 05:49:41 PM PDT 24 | 512566949 ps | ||
T421 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3743251756 | Jul 21 05:49:04 PM PDT 24 | Jul 21 05:49:06 PM PDT 24 | 111288254 ps | ||
T422 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3255893119 | Jul 21 05:49:32 PM PDT 24 | Jul 21 05:49:34 PM PDT 24 | 232682931 ps | ||
T423 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4286810688 | Jul 21 05:49:16 PM PDT 24 | Jul 21 05:49:17 PM PDT 24 | 235138818 ps | ||
T424 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2298685782 | Jul 21 05:49:47 PM PDT 24 | Jul 21 05:49:58 PM PDT 24 | 4352550469 ps | ||
T425 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3524189255 | Jul 21 05:49:30 PM PDT 24 | Jul 21 05:49:43 PM PDT 24 | 12272437842 ps | ||
T426 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3211753477 | Jul 21 05:49:23 PM PDT 24 | Jul 21 05:49:44 PM PDT 24 | 17774499520 ps | ||
T427 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.965834475 | Jul 21 05:49:29 PM PDT 24 | Jul 21 05:49:33 PM PDT 24 | 171704490 ps | ||
T428 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2479448937 | Jul 21 05:49:36 PM PDT 24 | Jul 21 05:49:45 PM PDT 24 | 511006553 ps | ||
T429 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3317984903 | Jul 21 05:49:04 PM PDT 24 | Jul 21 05:49:07 PM PDT 24 | 188234698 ps | ||
T430 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.569938947 | Jul 21 05:49:34 PM PDT 24 | Jul 21 05:49:39 PM PDT 24 | 3582114830 ps | ||
T431 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.590048920 | Jul 21 05:49:17 PM PDT 24 | Jul 21 05:49:19 PM PDT 24 | 986117295 ps | ||
T432 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3232161603 | Jul 21 05:49:28 PM PDT 24 | Jul 21 05:49:32 PM PDT 24 | 960166316 ps | ||
T433 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2543396637 | Jul 21 05:49:54 PM PDT 24 | Jul 21 05:50:12 PM PDT 24 | 7934256773 ps | ||
T434 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1016516404 | Jul 21 05:49:19 PM PDT 24 | Jul 21 05:50:39 PM PDT 24 | 26531136091 ps | ||
T435 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.404683184 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:35 PM PDT 24 | 158155689 ps | ||
T436 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3953647691 | Jul 21 05:49:32 PM PDT 24 | Jul 21 05:49:34 PM PDT 24 | 330176814 ps | ||
T437 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3332062493 | Jul 21 05:49:07 PM PDT 24 | Jul 21 05:49:12 PM PDT 24 | 203508134 ps | ||
T438 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2053691504 | Jul 21 05:49:22 PM PDT 24 | Jul 21 05:49:31 PM PDT 24 | 3640671512 ps | ||
T439 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1150588284 | Jul 21 05:49:36 PM PDT 24 | Jul 21 05:49:37 PM PDT 24 | 1719440545 ps | ||
T113 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.183651725 | Jul 21 05:49:38 PM PDT 24 | Jul 21 05:49:41 PM PDT 24 | 272214151 ps | ||
T440 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2973957190 | Jul 21 05:49:31 PM PDT 24 | Jul 21 05:49:33 PM PDT 24 | 221301255 ps | ||
T441 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1149421846 | Jul 21 05:49:42 PM PDT 24 | Jul 21 05:49:46 PM PDT 24 | 1768139972 ps | ||
T442 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1640133917 | Jul 21 05:49:29 PM PDT 24 | Jul 21 05:49:31 PM PDT 24 | 794212272 ps | ||
T443 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3934541125 | Jul 21 05:49:08 PM PDT 24 | Jul 21 05:49:11 PM PDT 24 | 2541084939 ps |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.1430800848 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 3248421905 ps |
CPU time | 4.48 seconds |
Started | Jul 21 07:06:18 PM PDT 24 |
Finished | Jul 21 07:06:23 PM PDT 24 |
Peak memory | 213044 kb |
Host | smart-afbcad48-e212-491f-a5f5-575dc42a43f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430800848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1430800848 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.85083787 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 10883558943 ps |
CPU time | 19.46 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:30 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-14273aff-a1b8-4fd9-b869-f6bcb3f4f208 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85083787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.85083787 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2647779620 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 4512881539 ps |
CPU time | 7.86 seconds |
Started | Jul 21 05:49:29 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 213888 kb |
Host | smart-28e9e298-e087-4d39-aa79-ace2c03acef3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647779620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2647779620 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2855777668 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 49147357716 ps |
CPU time | 124.54 seconds |
Started | Jul 21 05:49:12 PM PDT 24 |
Finished | Jul 21 05:51:17 PM PDT 24 |
Peak memory | 221976 kb |
Host | smart-dfb38938-884c-4174-a9d5-36eb70969980 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855777668 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2855777668 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.1045578324 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1649166652 ps |
CPU time | 2.32 seconds |
Started | Jul 21 07:06:20 PM PDT 24 |
Finished | Jul 21 07:06:23 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-f8eac5ad-4427-4baa-ae64-d7a21943a7c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045578324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1045578324 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.739631424 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 6594935645 ps |
CPU time | 32.95 seconds |
Started | Jul 21 05:49:16 PM PDT 24 |
Finished | Jul 21 05:49:49 PM PDT 24 |
Peak memory | 213764 kb |
Host | smart-20d569f5-08a8-4808-94d4-75fe42aaa64f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739631424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.739631424 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3471293295 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 14461033326 ps |
CPU time | 27.09 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:39 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-e9ceeacb-43ba-4027-a132-d00bd682278b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471293295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3471293295 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.328215194 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 5237706331 ps |
CPU time | 15.17 seconds |
Started | Jul 21 07:05:51 PM PDT 24 |
Finished | Jul 21 07:06:07 PM PDT 24 |
Peak memory | 214008 kb |
Host | smart-56d55273-5545-4f45-9ed6-be9e4a3aef7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328215194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.328215194 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.2466527509 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 38605000 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:05:49 PM PDT 24 |
Finished | Jul 21 07:05:56 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-63032267-dda2-4ffd-aba2-28d8fc287956 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466527509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2466527509 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1436251806 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 6659854141 ps |
CPU time | 33.76 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:51 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-3c9f2cfb-3594-4c6d-972b-6483ec3a93b2 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436251806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1436251806 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.3604728364 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 5745737204 ps |
CPU time | 3.3 seconds |
Started | Jul 21 07:05:37 PM PDT 24 |
Finished | Jul 21 07:05:42 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-b2f306b2-f051-44f9-b16e-7fd3e62d0503 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604728364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3604728364 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.1591490433 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 13424205709 ps |
CPU time | 13.57 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:40 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-e51a5b77-53ab-48a4-a896-cbc78b191a3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591490433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1591490433 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.143918254 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 7838364067 ps |
CPU time | 11.36 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:37 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-6cd6e50b-6ec9-40ab-9dc3-db520ab824aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143918254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.143918254 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.3533617941 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 78261762 ps |
CPU time | 0.86 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 215752 kb |
Host | smart-eb09e630-861d-4da8-9851-23cb526933ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533617941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3533617941 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1136297688 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 5802524768 ps |
CPU time | 8.09 seconds |
Started | Jul 21 07:05:36 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-9359d112-066f-423c-b623-09a61fac6774 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136297688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1136297688 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.677512238 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 953255762 ps |
CPU time | 2.63 seconds |
Started | Jul 21 07:05:50 PM PDT 24 |
Finished | Jul 21 07:05:53 PM PDT 24 |
Peak memory | 229316 kb |
Host | smart-2eec8197-b39c-4596-855b-1043af27e804 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677512238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.677512238 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.219661315 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 343560072 ps |
CPU time | 1.13 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-dd6ce3c9-3759-41a3-b00f-28c6d6102a12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219661315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.219661315 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.4191681049 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 196526975 ps |
CPU time | 0.96 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-6f26d835-c6cb-4e19-b266-fd5df6493f4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191681049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4191681049 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.4087366132 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 12142632822 ps |
CPU time | 15.78 seconds |
Started | Jul 21 07:06:02 PM PDT 24 |
Finished | Jul 21 07:06:18 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-80cd2ef9-0f4d-470b-834a-27be9b7ef826 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087366132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4087366132 |
Directory | /workspace/9.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.1778700949 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 2798893051 ps |
CPU time | 3.1 seconds |
Started | Jul 21 07:05:48 PM PDT 24 |
Finished | Jul 21 07:05:52 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-d78147e5-e34c-4018-a28f-a368045158ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778700949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1778700949 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.2590098346 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 97987126 ps |
CPU time | 0.89 seconds |
Started | Jul 21 07:05:36 PM PDT 24 |
Finished | Jul 21 07:05:39 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-1a2c9277-e167-40b2-87e0-2c97f9d21636 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590098346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2590098346 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1628446635 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1142097000 ps |
CPU time | 17.62 seconds |
Started | Jul 21 05:49:48 PM PDT 24 |
Finished | Jul 21 05:50:06 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-00b9e103-ce9f-4ebd-9854-378869984d3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628446635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1 628446635 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3765858802 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 4905745808 ps |
CPU time | 3.35 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:05:58 PM PDT 24 |
Peak memory | 213764 kb |
Host | smart-403331ef-7b57-4cba-9e20-975825135569 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765858802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3765858802 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.1307101164 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 4610075939 ps |
CPU time | 13.09 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:28 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-e741694b-6dcf-4360-be79-8f6cc4ca07ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307101164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1307101164 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4183114494 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 62666728907 ps |
CPU time | 403.84 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:56:15 PM PDT 24 |
Peak memory | 233436 kb |
Host | smart-c799d3ab-aa31-4b3c-9676-d062a5af566d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183114494 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.4183114494 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.39777970 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 6448228473 ps |
CPU time | 5.02 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:20 PM PDT 24 |
Peak memory | 212944 kb |
Host | smart-c02d0b09-3427-405b-9ce7-20ca0262d686 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39777970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.39777970 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.2242701800 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1123046433 ps |
CPU time | 1.54 seconds |
Started | Jul 21 07:05:45 PM PDT 24 |
Finished | Jul 21 07:05:48 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-1228f624-b21d-434c-baa6-c4dcd7612797 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242701800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2242701800 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2213769100 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1137061884 ps |
CPU time | 1.46 seconds |
Started | Jul 21 07:05:35 PM PDT 24 |
Finished | Jul 21 07:05:37 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-9653dabb-7005-42e2-98ed-67ccb8f60b1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213769100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2213769100 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2112841357 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 5968496582 ps |
CPU time | 8.8 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-23d52bc8-1394-4ed4-bc04-fb1c3603338d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112841357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2112841357 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.2037134459 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 4311436770 ps |
CPU time | 12.98 seconds |
Started | Jul 21 07:06:12 PM PDT 24 |
Finished | Jul 21 07:06:26 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-d67aa449-f548-44bf-a150-3fce2d1246d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037134459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2037134459 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.934888774 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 119014976 ps |
CPU time | 0.76 seconds |
Started | Jul 21 07:05:36 PM PDT 24 |
Finished | Jul 21 07:05:38 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-59073408-8f01-4477-a966-759489cfb5d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934888774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.934888774 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1673440561 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 7481493312 ps |
CPU time | 5.87 seconds |
Started | Jul 21 05:49:04 PM PDT 24 |
Finished | Jul 21 05:49:10 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-3ce5dec5-5fb2-4b2c-83a2-92cacb2b8ff3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673440561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.1673440561 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.781429088 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 5228145617 ps |
CPU time | 3 seconds |
Started | Jul 21 07:06:23 PM PDT 24 |
Finished | Jul 21 07:06:28 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-714e72a5-2f4a-4a7f-8569-4c7216e63e44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781429088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.781429088 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4227334163 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1782173140 ps |
CPU time | 7.81 seconds |
Started | Jul 21 05:49:14 PM PDT 24 |
Finished | Jul 21 05:49:22 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-9cbdeb10-c0e4-4077-bb6d-b9507a9105e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227334163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.4227334163 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.145941142 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 2292586887 ps |
CPU time | 20.78 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:56 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-172927dd-52c7-4afe-8150-5d7527cd8e54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145941142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.145941142 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.293455872 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 715309281 ps |
CPU time | 1.59 seconds |
Started | Jul 21 05:48:59 PM PDT 24 |
Finished | Jul 21 05:49:01 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-0a3aa927-e684-4147-9fcf-58a432ad0423 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293455872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _aliasing.293455872 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.674674149 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 231714317 ps |
CPU time | 1.52 seconds |
Started | Jul 21 05:49:46 PM PDT 24 |
Finished | Jul 21 05:49:48 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-00fa7855-8b3f-4292-9a13-e03cf6aad72b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674674149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.674674149 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2231247727 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 117982764 ps |
CPU time | 1.02 seconds |
Started | Jul 21 07:05:43 PM PDT 24 |
Finished | Jul 21 07:05:46 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-20437135-bc49-4a94-98c5-1caac28da8dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2231247727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2231247727 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3588474299 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 345683733 ps |
CPU time | 1.1 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-33c823f4-0de0-48af-ba0c-fc1336757dbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588474299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3588474299 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2283687103 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 41993908569 ps |
CPU time | 181.46 seconds |
Started | Jul 21 05:49:09 PM PDT 24 |
Finished | Jul 21 05:52:10 PM PDT 24 |
Peak memory | 220868 kb |
Host | smart-880b3e39-528c-4f2d-a443-e7d4a0ab58de |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283687103 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2283687103 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.515683668 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 2267879018 ps |
CPU time | 9.33 seconds |
Started | Jul 21 05:49:05 PM PDT 24 |
Finished | Jul 21 05:49:15 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-bf58517e-600c-490b-a77a-ba54e738909f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515683668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.515683668 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2605850750 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2766013149 ps |
CPU time | 10.72 seconds |
Started | Jul 21 05:49:39 PM PDT 24 |
Finished | Jul 21 05:49:50 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-5dc291c0-41a2-4d77-a475-9a7bf095e4e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605850750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 605850750 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3053697503 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 2224580099 ps |
CPU time | 26.16 seconds |
Started | Jul 21 05:48:58 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-dc9d92a7-d648-4710-93b8-c99093d58a0a |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053697503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.3053697503 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.36251384 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 6459025680 ps |
CPU time | 69.02 seconds |
Started | Jul 21 05:49:12 PM PDT 24 |
Finished | Jul 21 05:50:21 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-76219a15-7e0a-46f3-99e5-113012b1ff45 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36251384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.36251384 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3743251756 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 111288254 ps |
CPU time | 2.43 seconds |
Started | Jul 21 05:49:04 PM PDT 24 |
Finished | Jul 21 05:49:06 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-29f10eaf-24f3-48cb-a560-8be126f12e96 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743251756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3743251756 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4272408191 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 2028942402 ps |
CPU time | 2.68 seconds |
Started | Jul 21 05:49:05 PM PDT 24 |
Finished | Jul 21 05:49:08 PM PDT 24 |
Peak memory | 218996 kb |
Host | smart-7ce8ea6a-be0e-416f-99b0-c78504aa5437 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272408191 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.4272408191 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3317984903 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 188234698 ps |
CPU time | 2.36 seconds |
Started | Jul 21 05:49:04 PM PDT 24 |
Finished | Jul 21 05:49:07 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-205f9239-6719-445f-b079-4987ffce9ff6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317984903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3317984903 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1671337440 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 61667841537 ps |
CPU time | 55.33 seconds |
Started | Jul 21 05:49:06 PM PDT 24 |
Finished | Jul 21 05:50:02 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-cdc50e87-32cd-42e6-a4f0-9d4c9416e901 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671337440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1671337440 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1610890876 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 85140572014 ps |
CPU time | 63.14 seconds |
Started | Jul 21 05:49:06 PM PDT 24 |
Finished | Jul 21 05:50:09 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-30a17981-abe4-4a2c-af1d-622a95d84f4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610890876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.1610890876 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2346412971 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 2089757757 ps |
CPU time | 2.54 seconds |
Started | Jul 21 05:49:05 PM PDT 24 |
Finished | Jul 21 05:49:08 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-29215d51-e102-44ae-9cff-164c3b72581e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346412971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2346412971 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.763616679 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1184360654 ps |
CPU time | 1.67 seconds |
Started | Jul 21 05:49:06 PM PDT 24 |
Finished | Jul 21 05:49:08 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-7be3ae45-b9f6-4e99-a6c7-34c4bb55b80a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763616679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.763616679 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1548836793 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 9742895863 ps |
CPU time | 8.42 seconds |
Started | Jul 21 05:48:59 PM PDT 24 |
Finished | Jul 21 05:49:08 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-b36bea37-2f21-41c3-8b66-b6e8428fbec0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548836793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1548836793 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2798793132 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 172429959 ps |
CPU time | 1.23 seconds |
Started | Jul 21 05:49:02 PM PDT 24 |
Finished | Jul 21 05:49:04 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-2f957ef7-56fd-4877-b842-3192a4d79455 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798793132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2798793132 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1163991451 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 423602233 ps |
CPU time | 1.33 seconds |
Started | Jul 21 05:49:01 PM PDT 24 |
Finished | Jul 21 05:49:03 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-707a6f71-aa20-4f4d-8dec-c3f4fbfba966 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163991451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 163991451 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1913088939 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 78573824 ps |
CPU time | 0.75 seconds |
Started | Jul 21 05:49:05 PM PDT 24 |
Finished | Jul 21 05:49:07 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-f14f0609-9165-4a4b-8d88-73dda8d42560 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913088939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1913088939 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.413089219 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 47600937 ps |
CPU time | 0.69 seconds |
Started | Jul 21 05:49:12 PM PDT 24 |
Finished | Jul 21 05:49:13 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-5d4e5639-dd73-4088-bf56-36c563cc3772 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413089219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.413089219 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1190121714 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 578869345 ps |
CPU time | 4.18 seconds |
Started | Jul 21 05:49:10 PM PDT 24 |
Finished | Jul 21 05:49:15 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-8c8a04b3-93ec-444b-a13b-3c2e0b975154 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190121714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.1190121714 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.666856044 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 118200744 ps |
CPU time | 4.56 seconds |
Started | Jul 21 05:49:08 PM PDT 24 |
Finished | Jul 21 05:49:13 PM PDT 24 |
Peak memory | 213756 kb |
Host | smart-1d445072-a7ee-42e8-9612-b06d4669642e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666856044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.666856044 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1372380564 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 19560837187 ps |
CPU time | 34.45 seconds |
Started | Jul 21 05:49:06 PM PDT 24 |
Finished | Jul 21 05:49:41 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-36b1763c-417e-426a-91a8-a035717571e7 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372380564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.1372380564 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1910800142 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 6548685073 ps |
CPU time | 38.99 seconds |
Started | Jul 21 05:49:07 PM PDT 24 |
Finished | Jul 21 05:49:47 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-584d0f2e-5139-44b4-af9f-c72d522032a0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910800142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1910800142 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3129404881 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 351860970 ps |
CPU time | 1.71 seconds |
Started | Jul 21 05:49:06 PM PDT 24 |
Finished | Jul 21 05:49:08 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-888f1131-d696-4727-bbbb-7b19aed71833 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129404881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3129404881 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3248930403 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 2477749334 ps |
CPU time | 3.17 seconds |
Started | Jul 21 05:49:09 PM PDT 24 |
Finished | Jul 21 05:49:13 PM PDT 24 |
Peak memory | 221876 kb |
Host | smart-f24c2bf2-8e49-43f2-b398-06076f2f2ce0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248930403 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3248930403 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2046671743 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 113359671 ps |
CPU time | 1.58 seconds |
Started | Jul 21 05:49:05 PM PDT 24 |
Finished | Jul 21 05:49:07 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-8dec77c7-8009-412e-8f2c-c121eed6ecb4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046671743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2046671743 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.556336122 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 83596361439 ps |
CPU time | 113.61 seconds |
Started | Jul 21 05:49:06 PM PDT 24 |
Finished | Jul 21 05:51:00 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-9b33f49c-8d66-41f1-8e36-42d0a826ce55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556336122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _aliasing.556336122 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2335897373 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 14094489738 ps |
CPU time | 10.99 seconds |
Started | Jul 21 05:49:07 PM PDT 24 |
Finished | Jul 21 05:49:19 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-8fe57938-0509-4526-8f6c-a7989c399c4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335897373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2335897373 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4154549493 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 5989013999 ps |
CPU time | 15.57 seconds |
Started | Jul 21 05:49:10 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-c83a3a4e-a916-4d37-8bfd-d70957143e67 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154549493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4 154549493 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.803404237 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 1618265900 ps |
CPU time | 1.78 seconds |
Started | Jul 21 05:49:11 PM PDT 24 |
Finished | Jul 21 05:49:13 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-7889976b-d95f-48e5-ad1e-611179985ba4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803404237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _aliasing.803404237 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1382977005 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 34665375823 ps |
CPU time | 34.47 seconds |
Started | Jul 21 05:49:08 PM PDT 24 |
Finished | Jul 21 05:49:43 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-1832a46d-fb29-44d8-87bb-2ca5783394f7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382977005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1382977005 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3122269985 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 307388577 ps |
CPU time | 1.32 seconds |
Started | Jul 21 05:49:10 PM PDT 24 |
Finished | Jul 21 05:49:11 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-2303a6e8-faf3-47b6-92c6-2af6be05a705 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122269985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.3122269985 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4105233193 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 372531657 ps |
CPU time | 1.52 seconds |
Started | Jul 21 05:49:07 PM PDT 24 |
Finished | Jul 21 05:49:09 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-13add7e5-8dfc-4d2a-8bc9-59f527a80777 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105233193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4 105233193 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3765402907 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 77465036 ps |
CPU time | 0.78 seconds |
Started | Jul 21 05:49:07 PM PDT 24 |
Finished | Jul 21 05:49:09 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-aa3824b0-6888-461e-a49d-33467de0ed81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765402907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.3765402907 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2426524072 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 170303064 ps |
CPU time | 0.79 seconds |
Started | Jul 21 05:49:07 PM PDT 24 |
Finished | Jul 21 05:49:08 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-a643ba7d-e10f-401f-a792-3cc83e4a4797 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426524072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2426524072 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.196550859 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 41062047812 ps |
CPU time | 278.5 seconds |
Started | Jul 21 05:49:05 PM PDT 24 |
Finished | Jul 21 05:53:44 PM PDT 24 |
Peak memory | 222008 kb |
Host | smart-107edc47-a6b8-48c3-93c4-5c3e29cf02f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196550859 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.196550859 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3332062493 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 203508134 ps |
CPU time | 4.53 seconds |
Started | Jul 21 05:49:07 PM PDT 24 |
Finished | Jul 21 05:49:12 PM PDT 24 |
Peak memory | 213708 kb |
Host | smart-497785ac-28f2-474f-a590-ab71a62e8aa9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332062493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3332062493 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2888847493 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 2227883614 ps |
CPU time | 10.39 seconds |
Started | Jul 21 05:49:10 PM PDT 24 |
Finished | Jul 21 05:49:21 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-e4d7f211-95a9-4376-b6e7-787cfca9f083 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888847493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2888847493 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3610337895 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 420965398 ps |
CPU time | 3.88 seconds |
Started | Jul 21 05:49:33 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 221768 kb |
Host | smart-3144d61a-a7f6-47ae-b50c-63c0629cd7f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610337895 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3610337895 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2450362229 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 160280615 ps |
CPU time | 2.64 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:35 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-bb415597-dc00-4f7e-a0eb-4cd98d0e6dd4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450362229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2450362229 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3524189255 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 12272437842 ps |
CPU time | 12 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:43 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-6188fba5-5909-4663-9cf7-f627a632b96e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524189255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.3524189255 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1341243799 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 2125624244 ps |
CPU time | 6.24 seconds |
Started | Jul 21 05:49:28 PM PDT 24 |
Finished | Jul 21 05:49:34 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-2e3da746-9e20-4176-8660-c0e48febf057 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341243799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1341243799 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3255893119 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 232682931 ps |
CPU time | 1.04 seconds |
Started | Jul 21 05:49:32 PM PDT 24 |
Finished | Jul 21 05:49:34 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-3ac2cd5d-16d1-48d8-9a1f-ea48cea84544 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255893119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 3255893119 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2554327643 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 163883567 ps |
CPU time | 6.58 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:38 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-b9d97eed-983c-405f-b227-2e1dc795c472 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554327643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.2554327643 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3267165257 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 2144960217 ps |
CPU time | 8.89 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:40 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-3414704b-39e3-4ae6-b728-de4735e150ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267165257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3 267165257 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1776930702 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1875508605 ps |
CPU time | 3.78 seconds |
Started | Jul 21 05:49:37 PM PDT 24 |
Finished | Jul 21 05:49:41 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-e78ded1b-3cf6-4875-b530-7c096982b2a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776930702 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1776930702 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.332786926 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 127149393 ps |
CPU time | 2.43 seconds |
Started | Jul 21 05:49:36 PM PDT 24 |
Finished | Jul 21 05:49:39 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-e6263142-03ea-4beb-964c-955584d36e58 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332786926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.332786926 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.308296740 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 60999636 ps |
CPU time | 0.75 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-b04d57d3-fb3f-4c7f-a7d5-3286174110e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308296740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.308296740 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.207489564 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 5764581239 ps |
CPU time | 8.51 seconds |
Started | Jul 21 05:49:32 PM PDT 24 |
Finished | Jul 21 05:49:41 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-9406ebe1-b80a-45c6-b6f8-2d57241abbdd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207489564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.207489564 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3953647691 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 330176814 ps |
CPU time | 1.08 seconds |
Started | Jul 21 05:49:32 PM PDT 24 |
Finished | Jul 21 05:49:34 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-b02a34bc-b0b6-4fe3-84bc-65eb08be344d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953647691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3953647691 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1379925300 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 421547850 ps |
CPU time | 7.76 seconds |
Started | Jul 21 05:49:38 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-f8ba1749-a06c-4a80-a381-ae003b4d3b90 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379925300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.1379925300 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.965834475 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 171704490 ps |
CPU time | 3.16 seconds |
Started | Jul 21 05:49:29 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 221776 kb |
Host | smart-9b569bef-28e6-4bf8-b107-9f181536031e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965834475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.965834475 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.81523140 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 1470381802 ps |
CPU time | 8.81 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:40 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-c50310f9-639b-460e-94ab-2f75f024c318 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81523140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.81523140 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3004850750 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 2400897838 ps |
CPU time | 3.91 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:40 PM PDT 24 |
Peak memory | 218696 kb |
Host | smart-35c5875c-c9e3-4aa5-9ab0-c31e02b365e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004850750 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3004850750 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.183651725 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 272214151 ps |
CPU time | 2.56 seconds |
Started | Jul 21 05:49:38 PM PDT 24 |
Finished | Jul 21 05:49:41 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-fb3382b7-315b-4f99-8d8d-a8edb06d06d5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183651725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.183651725 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.476317363 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 5798990663 ps |
CPU time | 17.03 seconds |
Started | Jul 21 05:49:34 PM PDT 24 |
Finished | Jul 21 05:49:52 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-6dda49a8-8237-4816-a28a-c7fe33c20591 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476317363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rv_dm_jtag_dmi_csr_bit_bash.476317363 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1150588284 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1719440545 ps |
CPU time | 1.51 seconds |
Started | Jul 21 05:49:36 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-5e01f856-a9d1-4d34-8bf0-c214b76156a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150588284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 1150588284 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3505521794 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 244455479 ps |
CPU time | 0.98 seconds |
Started | Jul 21 05:49:45 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-4d80186f-d2a2-4c00-a702-32c6ca5f2315 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505521794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 3505521794 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1145954937 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 747335757 ps |
CPU time | 6.25 seconds |
Started | Jul 21 05:49:44 PM PDT 24 |
Finished | Jul 21 05:49:51 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-b8629990-bb03-4e9d-be46-66944163cd15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145954937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1145954937 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2180902402 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 133932696 ps |
CPU time | 3.75 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:39 PM PDT 24 |
Peak memory | 213756 kb |
Host | smart-a4dd9633-b669-4f8c-9a1a-4f6ca42f89a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180902402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2180902402 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2173066649 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 8455188162 ps |
CPU time | 22.92 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:58 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-b6e68abf-c218-4a76-8acc-d995f0c77247 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173066649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2 173066649 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.906246963 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 120091449 ps |
CPU time | 2.44 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:38 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-f0489f5f-415a-45dc-b43b-615e01bea36e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906246963 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.906246963 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3818104252 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 107321836 ps |
CPU time | 2.26 seconds |
Started | Jul 21 05:49:34 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-f050a6fc-3492-4678-8a14-2eefa11053fa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818104252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3818104252 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3793189522 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 19654407895 ps |
CPU time | 57.85 seconds |
Started | Jul 21 05:49:34 PM PDT 24 |
Finished | Jul 21 05:50:32 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-d4e4a6d6-52f4-413a-8a54-c7f59fb0c188 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793189522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.3793189522 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.569938947 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 3582114830 ps |
CPU time | 4.14 seconds |
Started | Jul 21 05:49:34 PM PDT 24 |
Finished | Jul 21 05:49:39 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-7244c149-e130-4135-bdc5-9e6125e62798 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569938947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.569938947 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1617445481 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 679740880 ps |
CPU time | 1.66 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-feaf0b5d-af57-4f3e-9997-3ed7072a5ab5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617445481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 1617445481 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2479448937 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 511006553 ps |
CPU time | 8.01 seconds |
Started | Jul 21 05:49:36 PM PDT 24 |
Finished | Jul 21 05:49:45 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-943960e4-6b06-49df-b4d3-26f7908e4d83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479448937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2479448937 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.793259927 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 68861835 ps |
CPU time | 2.24 seconds |
Started | Jul 21 05:49:34 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-a040c2df-13a9-48ba-8885-a22fdc52c359 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793259927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.793259927 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2027377024 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 201736655 ps |
CPU time | 2.53 seconds |
Started | Jul 21 05:49:40 PM PDT 24 |
Finished | Jul 21 05:49:43 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-88460859-5c7d-4a14-ac76-0263158531c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027377024 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2027377024 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3542614527 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 120757536 ps |
CPU time | 1.49 seconds |
Started | Jul 21 05:49:38 PM PDT 24 |
Finished | Jul 21 05:49:40 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-ac1d8021-69ed-41f7-a927-1c94cbf35ba6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542614527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3542614527 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1571151714 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 9992958671 ps |
CPU time | 10.59 seconds |
Started | Jul 21 05:49:35 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-dbe17883-d1a8-4d30-abcd-ac7dc1dadd42 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571151714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.1571151714 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3776881174 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 2812725561 ps |
CPU time | 4.98 seconds |
Started | Jul 21 05:49:37 PM PDT 24 |
Finished | Jul 21 05:49:42 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-66f5748c-8111-4141-8f75-42d29ebb7f6d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776881174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3776881174 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2924667297 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 512566949 ps |
CPU time | 2.05 seconds |
Started | Jul 21 05:49:39 PM PDT 24 |
Finished | Jul 21 05:49:41 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-ba75d909-3472-459b-8ec8-dc73dc5515a1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924667297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 2924667297 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.468039952 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 403836447 ps |
CPU time | 3.79 seconds |
Started | Jul 21 05:49:43 PM PDT 24 |
Finished | Jul 21 05:49:47 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-740c7083-551e-4772-8a72-3b1e8b0424b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468039952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.468039952 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.978652384 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 648010824 ps |
CPU time | 5.09 seconds |
Started | Jul 21 05:49:37 PM PDT 24 |
Finished | Jul 21 05:49:43 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-6949c89f-0feb-4021-947c-6aeb156b1a83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978652384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.978652384 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1541602855 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 1724927119 ps |
CPU time | 6.26 seconds |
Started | Jul 21 05:49:54 PM PDT 24 |
Finished | Jul 21 05:50:01 PM PDT 24 |
Peak memory | 221464 kb |
Host | smart-520bb8cb-a6cf-4a81-bc97-55f1750525b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541602855 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1541602855 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.492613790 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 188831486 ps |
CPU time | 2.4 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:49:44 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-bba978ca-7d85-4434-a882-8cb519134888 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492613790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.492613790 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2865556143 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 35252143749 ps |
CPU time | 91.54 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:51:14 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-2956aaa2-b0c4-4cdf-a9f2-f18a1746bc20 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865556143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.2865556143 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1149421846 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 1768139972 ps |
CPU time | 3.33 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-65080b8f-26f3-41ee-b4a5-01a499050caf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149421846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 1149421846 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3527728140 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 218375003 ps |
CPU time | 1.07 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:49:43 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-eb6971cb-9da6-498c-81be-99926aa6ae89 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527728140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3527728140 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2673740013 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 2072285747 ps |
CPU time | 4.63 seconds |
Started | Jul 21 05:49:40 PM PDT 24 |
Finished | Jul 21 05:49:45 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-1b89c12c-9a5d-4fcb-9382-64874b0707fd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673740013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.2673740013 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.645805373 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 424097032 ps |
CPU time | 2.71 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:49:44 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-7f29cdd8-92c1-4490-a2de-8c38c8bd4269 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645805373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.645805373 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.299778556 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1398065839 ps |
CPU time | 20.39 seconds |
Started | Jul 21 05:49:55 PM PDT 24 |
Finished | Jul 21 05:50:16 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-52de645a-11f4-48d7-8345-dbd85ed1c670 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299778556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.299778556 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.638762519 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 403285513 ps |
CPU time | 4.9 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:49:48 PM PDT 24 |
Peak memory | 220516 kb |
Host | smart-c761c22d-66a6-496f-864d-22af3b0b494f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638762519 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.638762519 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2755138699 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 287553775 ps |
CPU time | 1.67 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:49:44 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-33dc580f-cc60-474d-af92-06c56358d7aa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755138699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2755138699 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.395797251 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 18649877649 ps |
CPU time | 22.71 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:50:04 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-1bd38636-c628-4285-937d-9e5aa3d53395 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395797251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rv_dm_jtag_dmi_csr_bit_bash.395797251 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1721725240 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 2569500154 ps |
CPU time | 7.44 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:49:49 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-fc0fda27-4081-4a18-8e5a-388ffc5257cc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721725240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 1721725240 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.307175572 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 123089977 ps |
CPU time | 1.04 seconds |
Started | Jul 21 05:49:40 PM PDT 24 |
Finished | Jul 21 05:49:42 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-e60cce29-a483-4c1c-ab88-1229a9dab1cf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307175572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.307175572 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1759434269 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1701390009 ps |
CPU time | 7.6 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:49:50 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-5107e103-411c-4c26-9da8-1cc8e6cb8603 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759434269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.1759434269 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2541332696 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 92350349 ps |
CPU time | 1.8 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:49:43 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-88fee218-4f67-4dae-8c9a-dfa8b1a4538b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541332696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2541332696 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2398407669 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 4576737208 ps |
CPU time | 9.83 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:49:52 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-3d13d53c-42a6-4c12-8273-5ef7c1c8eb43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398407669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2 398407669 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.957343694 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 195127544 ps |
CPU time | 2.12 seconds |
Started | Jul 21 05:49:42 PM PDT 24 |
Finished | Jul 21 05:49:45 PM PDT 24 |
Peak memory | 217132 kb |
Host | smart-8f347edc-9995-45f1-8201-b7293bcd4232 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957343694 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.957343694 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1795426349 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 166380076 ps |
CPU time | 1.66 seconds |
Started | Jul 21 05:49:43 PM PDT 24 |
Finished | Jul 21 05:49:45 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-6a12c77f-1c0f-441e-a21f-e3bc70ed046c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795426349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1795426349 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3121632609 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 39695053 ps |
CPU time | 0.72 seconds |
Started | Jul 21 05:49:39 PM PDT 24 |
Finished | Jul 21 05:49:40 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-14b0faa1-7bfb-409c-9c74-f38c1859c15d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121632609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3121632609 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2543396637 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 7934256773 ps |
CPU time | 16.64 seconds |
Started | Jul 21 05:49:54 PM PDT 24 |
Finished | Jul 21 05:50:12 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-abb11145-863c-45dd-b501-45b972b01192 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543396637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 2543396637 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1755058450 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 188257980 ps |
CPU time | 1.18 seconds |
Started | Jul 21 05:49:41 PM PDT 24 |
Finished | Jul 21 05:49:42 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-376a275e-d81c-4144-a760-bdc7707645c5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755058450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1755058450 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2139206948 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 1120598921 ps |
CPU time | 7.8 seconds |
Started | Jul 21 05:49:55 PM PDT 24 |
Finished | Jul 21 05:50:03 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-a9581a9c-0c70-4152-9e0b-ed2243835d4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139206948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2139206948 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.262905237 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 112281979 ps |
CPU time | 4.46 seconds |
Started | Jul 21 05:49:54 PM PDT 24 |
Finished | Jul 21 05:50:00 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-6d4af4f4-d8a0-47b4-aa21-28c87f51ea67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262905237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.262905237 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.599535569 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 2657523007 ps |
CPU time | 17.35 seconds |
Started | Jul 21 05:49:54 PM PDT 24 |
Finished | Jul 21 05:50:12 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-2ce82e7b-9329-4ce6-9217-be36f8b9e8da |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599535569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.599535569 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2298685782 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 4352550469 ps |
CPU time | 10.42 seconds |
Started | Jul 21 05:49:47 PM PDT 24 |
Finished | Jul 21 05:49:58 PM PDT 24 |
Peak memory | 220556 kb |
Host | smart-28f26f6b-f8f0-4d41-a55e-653a9e509816 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298685782 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2298685782 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.50923271 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 908159655 ps |
CPU time | 1.82 seconds |
Started | Jul 21 05:49:45 PM PDT 24 |
Finished | Jul 21 05:49:48 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-f71a1dbb-0c08-428d-9c45-c8228e522eb1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50923271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.50923271 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1525965830 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 32407309803 ps |
CPU time | 23.77 seconds |
Started | Jul 21 05:49:47 PM PDT 24 |
Finished | Jul 21 05:50:12 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-41ea35e3-12af-469d-9444-6bbf92637c98 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525965830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1525965830 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.247636315 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 4591329218 ps |
CPU time | 13.42 seconds |
Started | Jul 21 05:49:46 PM PDT 24 |
Finished | Jul 21 05:50:00 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-ae56781d-7aca-4db5-96e2-39187b803f92 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247636315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.247636315 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2862761108 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 167096239 ps |
CPU time | 0.77 seconds |
Started | Jul 21 05:49:54 PM PDT 24 |
Finished | Jul 21 05:49:56 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-e0109c3d-8058-4328-9b28-3b3ab5602e2e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862761108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 2862761108 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2300986896 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 402600347 ps |
CPU time | 4.43 seconds |
Started | Jul 21 05:49:46 PM PDT 24 |
Finished | Jul 21 05:49:51 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-42d17195-67e2-4206-a6fe-b5c1c0001cbe |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300986896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2300986896 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3705713533 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 93170939 ps |
CPU time | 3.22 seconds |
Started | Jul 21 05:49:44 PM PDT 24 |
Finished | Jul 21 05:49:48 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-9996b230-f469-489c-ac38-d65cdd3f337d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705713533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3705713533 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1854610082 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 970687845 ps |
CPU time | 4.03 seconds |
Started | Jul 21 05:49:46 PM PDT 24 |
Finished | Jul 21 05:49:51 PM PDT 24 |
Peak memory | 216116 kb |
Host | smart-3e576c56-7565-4da3-936f-fb763080ff2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854610082 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1854610082 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1801091046 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 4035210034 ps |
CPU time | 10.19 seconds |
Started | Jul 21 05:49:45 PM PDT 24 |
Finished | Jul 21 05:49:55 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-b1fab21a-30ae-4dd3-9267-75d18136c387 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801091046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1801091046 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2353100213 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 904129045 ps |
CPU time | 3.49 seconds |
Started | Jul 21 05:49:45 PM PDT 24 |
Finished | Jul 21 05:49:49 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-1cc43bc0-4b1c-47da-9238-37aa506c359e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353100213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2353100213 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1413340420 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 896049156 ps |
CPU time | 2.01 seconds |
Started | Jul 21 05:49:45 PM PDT 24 |
Finished | Jul 21 05:49:48 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-9ca85809-cc6e-4f03-83d0-c9e040146988 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413340420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 1413340420 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.299714644 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 602656652 ps |
CPU time | 4.46 seconds |
Started | Jul 21 05:49:47 PM PDT 24 |
Finished | Jul 21 05:49:52 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-dc36c7c9-f4ba-4bc6-bf98-070eb6782b9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299714644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_ csr_outstanding.299714644 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3677212783 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 121317145 ps |
CPU time | 2.8 seconds |
Started | Jul 21 05:49:47 PM PDT 24 |
Finished | Jul 21 05:49:50 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-eb9dcaa9-c708-4dae-81ad-898237dcae88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677212783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3677212783 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2741426456 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 3554508824 ps |
CPU time | 22.13 seconds |
Started | Jul 21 05:49:45 PM PDT 24 |
Finished | Jul 21 05:50:08 PM PDT 24 |
Peak memory | 213708 kb |
Host | smart-b4459284-b611-484b-b9f6-b658c2374541 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741426456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2 741426456 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4154925691 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 16250251073 ps |
CPU time | 81.85 seconds |
Started | Jul 21 05:49:10 PM PDT 24 |
Finished | Jul 21 05:50:33 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-28eaae9f-5cfa-4ea0-b7a4-dd0475b2e4ed |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154925691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.4154925691 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3374880372 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 33185246448 ps |
CPU time | 79 seconds |
Started | Jul 21 05:49:11 PM PDT 24 |
Finished | Jul 21 05:50:30 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-46a09abe-f0a5-4444-a6c8-91866e2cc6de |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374880372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3374880372 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.409168305 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 367624987 ps |
CPU time | 3.23 seconds |
Started | Jul 21 05:49:13 PM PDT 24 |
Finished | Jul 21 05:49:16 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-f6e79ae1-fdf6-46ec-9953-9eefd1e61f72 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409168305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.409168305 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.599696958 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 956277368 ps |
CPU time | 3.97 seconds |
Started | Jul 21 05:49:20 PM PDT 24 |
Finished | Jul 21 05:49:24 PM PDT 24 |
Peak memory | 219940 kb |
Host | smart-ab5d0f0f-1e18-41a2-bc84-793eadf205cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599696958 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.599696958 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3623452969 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 99892843 ps |
CPU time | 1.65 seconds |
Started | Jul 21 05:49:13 PM PDT 24 |
Finished | Jul 21 05:49:15 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-ec054f97-e644-4125-80ac-a89470175136 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623452969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3623452969 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2493907010 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 84230543733 ps |
CPU time | 122.02 seconds |
Started | Jul 21 05:49:12 PM PDT 24 |
Finished | Jul 21 05:51:15 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-0e069231-a2a4-4707-bf6c-7f9dc975b997 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493907010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2493907010 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.871031351 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 27178814072 ps |
CPU time | 14.96 seconds |
Started | Jul 21 05:49:15 PM PDT 24 |
Finished | Jul 21 05:49:30 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-deeeb4b4-5e7e-41e8-934d-ccb35943502b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871031351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r v_dm_jtag_dmi_csr_bit_bash.871031351 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1199271007 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 2240616497 ps |
CPU time | 7.45 seconds |
Started | Jul 21 05:49:10 PM PDT 24 |
Finished | Jul 21 05:49:17 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-59d350eb-b4b4-4a47-90aa-939b0d3e248d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199271007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1199271007 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.37380839 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1796957219 ps |
CPU time | 5.39 seconds |
Started | Jul 21 05:49:15 PM PDT 24 |
Finished | Jul 21 05:49:21 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-b89079a2-06cd-4c0d-a22d-b3d21e663956 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37380839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.37380839 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3148813866 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 434713455 ps |
CPU time | 0.97 seconds |
Started | Jul 21 05:49:11 PM PDT 24 |
Finished | Jul 21 05:49:12 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-45f253a7-d9d3-4a37-a32b-bd46db76674c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148813866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.3148813866 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3934541125 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 2541084939 ps |
CPU time | 3.01 seconds |
Started | Jul 21 05:49:08 PM PDT 24 |
Finished | Jul 21 05:49:11 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-abffe73b-a048-4993-a512-9a86067d23fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934541125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.3934541125 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1746976355 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 130528130 ps |
CPU time | 0.97 seconds |
Started | Jul 21 05:49:12 PM PDT 24 |
Finished | Jul 21 05:49:13 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-5ed06e15-27b9-40ac-b2d5-5dce391affdc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746976355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.1746976355 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1176569943 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 684657850 ps |
CPU time | 0.89 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:19 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-d3aeb84b-537f-4f34-9e39-d581c13d2bd5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176569943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 176569943 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4286810688 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 235138818 ps |
CPU time | 0.78 seconds |
Started | Jul 21 05:49:16 PM PDT 24 |
Finished | Jul 21 05:49:17 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-6d3a6369-9b18-4c22-b2be-883cf94d8169 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286810688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.4286810688 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2949875209 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 173064932 ps |
CPU time | 0.78 seconds |
Started | Jul 21 05:49:15 PM PDT 24 |
Finished | Jul 21 05:49:16 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-879baf78-2482-4d43-aed3-7672f8dfef31 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949875209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2949875209 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1427650991 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 221595246 ps |
CPU time | 3.68 seconds |
Started | Jul 21 05:49:19 PM PDT 24 |
Finished | Jul 21 05:49:23 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-71e9c4b3-eadf-4519-9209-287dd98b86c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427650991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1427650991 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2902097792 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 472320208 ps |
CPU time | 2.35 seconds |
Started | Jul 21 05:49:14 PM PDT 24 |
Finished | Jul 21 05:49:17 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-b9daa7aa-518e-448f-a649-ab19cf939d8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902097792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2902097792 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2917923659 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 1748437111 ps |
CPU time | 20.45 seconds |
Started | Jul 21 05:49:16 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-d553be31-4425-4573-b957-4fddc37b4776 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917923659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2917923659 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3171230751 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 1566198775 ps |
CPU time | 28.72 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-3a54e8ca-d894-4b94-b65c-a8f476ddec26 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171230751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3171230751 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.949294763 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 475240199 ps |
CPU time | 2.49 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:20 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-95333337-e989-400f-b19e-14e020b74bbb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949294763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.949294763 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3794779467 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 1667303703 ps |
CPU time | 5.66 seconds |
Started | Jul 21 05:49:16 PM PDT 24 |
Finished | Jul 21 05:49:22 PM PDT 24 |
Peak memory | 219620 kb |
Host | smart-94b30392-4ca8-46c5-8b2f-16a598aab50f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794779467 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3794779467 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3497962306 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 176679516 ps |
CPU time | 2.61 seconds |
Started | Jul 21 05:49:19 PM PDT 24 |
Finished | Jul 21 05:49:22 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-54e7fbff-99a0-4cd7-9850-b6227cc4a29c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497962306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3497962306 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3300659918 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 72889454968 ps |
CPU time | 53.44 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:50:11 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-80ce726f-c65a-41f1-8e40-669d42bb78b5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300659918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.3300659918 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2732525641 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 1785415114 ps |
CPU time | 5.87 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:24 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-b5f9875d-afe1-44b6-8d24-32680409bf57 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732525641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.2732525641 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2836040242 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 4392746900 ps |
CPU time | 7.69 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-d952a808-cc59-4b4c-a7d4-01c13ccd035c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836040242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2836040242 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1918556552 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 1424968285 ps |
CPU time | 2.64 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:21 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-29d5c0e4-d68c-4533-8201-1e905cdc9cf6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918556552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 918556552 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.487968566 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 2329043667 ps |
CPU time | 1.4 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:19 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-297b99b5-7ab3-423f-9a7d-8ecdd50006f2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487968566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _aliasing.487968566 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.880472716 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 16486583149 ps |
CPU time | 42.04 seconds |
Started | Jul 21 05:49:18 PM PDT 24 |
Finished | Jul 21 05:50:01 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-cb017884-5ade-4afe-966b-2f82d224682c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880472716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _bit_bash.880472716 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3836754115 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 422680931 ps |
CPU time | 0.81 seconds |
Started | Jul 21 05:49:34 PM PDT 24 |
Finished | Jul 21 05:49:35 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-cca9b007-eb1a-4429-9259-16a34ffcdaab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836754115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3836754115 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.590048920 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 986117295 ps |
CPU time | 1.34 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:19 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-dc00bb00-8900-4ba7-b764-f2f65054a4b1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590048920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.590048920 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2848600198 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 116798786 ps |
CPU time | 0.74 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:18 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-8a26a9de-762e-4f8a-96ac-274045067e94 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848600198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.2848600198 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1500269033 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 40286839 ps |
CPU time | 0.69 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:18 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-0f1181e4-866c-4087-b11c-665b1f9885cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500269033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1500269033 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3711434894 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2376046316 ps |
CPU time | 7.11 seconds |
Started | Jul 21 05:49:18 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-4ae9a416-f55e-49c3-97ae-251e6ab4f456 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711434894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.3711434894 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1563922459 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 46075421995 ps |
CPU time | 176.03 seconds |
Started | Jul 21 05:49:16 PM PDT 24 |
Finished | Jul 21 05:52:13 PM PDT 24 |
Peak memory | 221988 kb |
Host | smart-dde9f0e1-4d1c-46e2-9a4a-5bb261f8f50e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563922459 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1563922459 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2532225599 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 400222016 ps |
CPU time | 3.35 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:21 PM PDT 24 |
Peak memory | 213784 kb |
Host | smart-522f01cd-cfe8-411b-8128-ac4a80ef5d8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532225599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2532225599 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2516231747 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 3375402180 ps |
CPU time | 73.42 seconds |
Started | Jul 21 05:49:20 PM PDT 24 |
Finished | Jul 21 05:50:33 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-3292cb04-384c-4ef2-a6ad-e6b7b16d2e59 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516231747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2516231747 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1919888213 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 15121124508 ps |
CPU time | 76.51 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:50:48 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-924789a6-2be6-4d33-a945-b9463c7f0477 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919888213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1919888213 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3685909415 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 187306182 ps |
CPU time | 2.45 seconds |
Started | Jul 21 05:49:26 PM PDT 24 |
Finished | Jul 21 05:49:29 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-4b3410e9-7afb-4ff8-88b3-3b496eacd2b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685909415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3685909415 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.333933660 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 2466321385 ps |
CPU time | 4.11 seconds |
Started | Jul 21 05:49:22 PM PDT 24 |
Finished | Jul 21 05:49:27 PM PDT 24 |
Peak memory | 218360 kb |
Host | smart-e5103f47-b62f-4c42-bf20-6fb40ff047b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333933660 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.333933660 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.345150132 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 109368047 ps |
CPU time | 1.45 seconds |
Started | Jul 21 05:49:25 PM PDT 24 |
Finished | Jul 21 05:49:27 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-f211ef8f-ccf4-4c1a-b604-ccbd57871f67 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345150132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.345150132 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1950947314 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 88961123745 ps |
CPU time | 213.85 seconds |
Started | Jul 21 05:49:14 PM PDT 24 |
Finished | Jul 21 05:52:49 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-14f51b9f-c480-42b5-887d-32074a047f8e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950947314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.1950947314 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2682895102 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 52698691260 ps |
CPU time | 144.78 seconds |
Started | Jul 21 05:49:15 PM PDT 24 |
Finished | Jul 21 05:51:40 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-35416d05-af1b-4733-a5f0-e38f31eb926f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682895102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.2682895102 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2891981166 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 15960569783 ps |
CPU time | 10.87 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:29 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-29c9e5df-2be4-45ea-9cd5-6f0936a23306 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891981166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2891981166 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3670233896 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 12132308463 ps |
CPU time | 30 seconds |
Started | Jul 21 05:49:15 PM PDT 24 |
Finished | Jul 21 05:49:45 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-64be9faf-ef0c-496a-8d5b-fbe79fba02fd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670233896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 670233896 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2842749070 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1073027237 ps |
CPU time | 1.5 seconds |
Started | Jul 21 05:49:19 PM PDT 24 |
Finished | Jul 21 05:49:21 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-775e9cc8-8991-4fb8-b806-1113eb0f8cdb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842749070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.2842749070 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.760027838 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2673396462 ps |
CPU time | 7.32 seconds |
Started | Jul 21 05:49:19 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-cd8efc39-cd22-46ab-9ba0-e3f75e3aa0eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760027838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.760027838 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2987126009 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 332072511 ps |
CPU time | 1.09 seconds |
Started | Jul 21 05:49:17 PM PDT 24 |
Finished | Jul 21 05:49:19 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-b8166696-77d3-4765-8b4d-e587e0b02bfb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987126009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.2987126009 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1495171359 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 130997125 ps |
CPU time | 0.84 seconds |
Started | Jul 21 05:49:18 PM PDT 24 |
Finished | Jul 21 05:49:19 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-fb0995dd-459c-4259-90e7-e691cb4ebdb4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495171359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 495171359 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.36526867 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 109521659 ps |
CPU time | 0.69 seconds |
Started | Jul 21 05:49:23 PM PDT 24 |
Finished | Jul 21 05:49:24 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-c4e75663-56b0-46a3-9774-c5a2aba4a791 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_parti al_access.36526867 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3842153536 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 39950403 ps |
CPU time | 0.75 seconds |
Started | Jul 21 05:49:21 PM PDT 24 |
Finished | Jul 21 05:49:22 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-06ce5860-df6c-4285-a68a-8063e02aec57 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842153536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3842153536 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.311778530 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 837166079 ps |
CPU time | 6.6 seconds |
Started | Jul 21 05:49:25 PM PDT 24 |
Finished | Jul 21 05:49:32 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-63782b0e-569b-4aaa-a0da-08921cf371c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311778530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c sr_outstanding.311778530 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1016516404 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 26531136091 ps |
CPU time | 79.76 seconds |
Started | Jul 21 05:49:19 PM PDT 24 |
Finished | Jul 21 05:50:39 PM PDT 24 |
Peak memory | 214768 kb |
Host | smart-af1c2f55-e095-4358-b3c4-9620bc32ed75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016516404 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1016516404 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1376886180 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 83203419 ps |
CPU time | 3.66 seconds |
Started | Jul 21 05:49:22 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-7b35a612-09cb-4096-91c2-7734f566c526 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376886180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1376886180 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.793509571 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 3319221228 ps |
CPU time | 17.48 seconds |
Started | Jul 21 05:49:23 PM PDT 24 |
Finished | Jul 21 05:49:41 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-e78f38ea-fa23-429a-8741-b987f33d3cb7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793509571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.793509571 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1248255181 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 57019828 ps |
CPU time | 2.4 seconds |
Started | Jul 21 05:49:22 PM PDT 24 |
Finished | Jul 21 05:49:25 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-38dd9b12-a06b-4d0b-9c56-7a022c136cae |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248255181 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1248255181 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4213854309 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 140927131 ps |
CPU time | 1.49 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-9cb632e7-0c53-4609-9900-e2114d5d4f51 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213854309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4213854309 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2388261846 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 5628050259 ps |
CPU time | 8.3 seconds |
Started | Jul 21 05:49:25 PM PDT 24 |
Finished | Jul 21 05:49:34 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-11462336-f678-4a9a-aff6-ec168842c93d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388261846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.2388261846 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3279137854 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 6426587474 ps |
CPU time | 4.9 seconds |
Started | Jul 21 05:49:22 PM PDT 24 |
Finished | Jul 21 05:49:28 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-c4f43aee-b680-4fec-a650-067a3a82feac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279137854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 279137854 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2560684659 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 265169387 ps |
CPU time | 1.38 seconds |
Started | Jul 21 05:49:21 PM PDT 24 |
Finished | Jul 21 05:49:23 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-66db94c5-e1a9-404d-9fa6-3a7ebfd27dc4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560684659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 560684659 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3270942193 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 932094601 ps |
CPU time | 7.44 seconds |
Started | Jul 21 05:49:23 PM PDT 24 |
Finished | Jul 21 05:49:30 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-c5550ce1-d6f1-4dce-a69f-5f9e5319ff35 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270942193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3270942193 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3853290685 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 22919237141 ps |
CPU time | 21.67 seconds |
Started | Jul 21 05:49:26 PM PDT 24 |
Finished | Jul 21 05:49:48 PM PDT 24 |
Peak memory | 220940 kb |
Host | smart-ae606fae-4d56-4cca-bc90-f97b71ecf344 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853290685 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3853290685 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.891745462 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 184627083 ps |
CPU time | 2.09 seconds |
Started | Jul 21 05:49:23 PM PDT 24 |
Finished | Jul 21 05:49:25 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-9566f50f-5342-40cc-bbb4-4637608afdd3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891745462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.891745462 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3620643794 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 4463953373 ps |
CPU time | 23.3 seconds |
Started | Jul 21 05:49:22 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-c9b1ca9e-1ea5-4fcb-a7d4-461f00d328ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620643794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3620643794 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2263568666 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 312075524 ps |
CPU time | 2.77 seconds |
Started | Jul 21 05:49:25 PM PDT 24 |
Finished | Jul 21 05:49:28 PM PDT 24 |
Peak memory | 218864 kb |
Host | smart-7d2f2aca-c3a4-4e4a-90de-4761e5f91222 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263568666 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2263568666 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1301923553 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 260310609 ps |
CPU time | 1.61 seconds |
Started | Jul 21 05:49:26 PM PDT 24 |
Finished | Jul 21 05:49:27 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-aa75bcd0-230a-4ae3-b589-9281039d7022 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301923553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1301923553 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3211753477 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 17774499520 ps |
CPU time | 20.31 seconds |
Started | Jul 21 05:49:23 PM PDT 24 |
Finished | Jul 21 05:49:44 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-357d8b8f-99e1-401e-bda3-db55f1b8caa5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211753477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.3211753477 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3431118995 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 6565739102 ps |
CPU time | 9.64 seconds |
Started | Jul 21 05:49:21 PM PDT 24 |
Finished | Jul 21 05:49:31 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-284aefba-2f13-496b-b089-be1d768ff7f6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431118995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 431118995 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.733588388 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 444173486 ps |
CPU time | 0.8 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:32 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-de66d1ae-837f-4266-b3c5-715bf309bbbf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733588388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.733588388 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3430146122 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 114363806 ps |
CPU time | 3.62 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:36 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-3442d75f-dee8-4f11-981b-fb8fd2e9b432 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430146122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.3430146122 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.676252204 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 276371122 ps |
CPU time | 4.77 seconds |
Started | Jul 21 05:49:25 PM PDT 24 |
Finished | Jul 21 05:49:30 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-2e80e826-d892-43d0-bec3-e304733fa9d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676252204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.676252204 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2152591521 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 6806701127 ps |
CPU time | 24.92 seconds |
Started | Jul 21 05:49:24 PM PDT 24 |
Finished | Jul 21 05:49:49 PM PDT 24 |
Peak memory | 213760 kb |
Host | smart-16698231-3a9f-4158-9489-02a34c4471c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152591521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2152591521 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1884324893 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 503025129 ps |
CPU time | 2.32 seconds |
Started | Jul 21 05:49:29 PM PDT 24 |
Finished | Jul 21 05:49:32 PM PDT 24 |
Peak memory | 216864 kb |
Host | smart-e1560e79-3e56-4479-8995-a825d768e9cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884324893 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1884324893 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.641902309 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 185676207 ps |
CPU time | 2.33 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:34 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-60c77e8f-fd4b-4944-ae9d-cea9f3b21823 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641902309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.641902309 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2053691504 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 3640671512 ps |
CPU time | 9.26 seconds |
Started | Jul 21 05:49:22 PM PDT 24 |
Finished | Jul 21 05:49:31 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-9906f15b-5f62-48f7-8750-55a34ae7dad4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053691504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.2053691504 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3974147274 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 1281387489 ps |
CPU time | 1.9 seconds |
Started | Jul 21 05:49:24 PM PDT 24 |
Finished | Jul 21 05:49:26 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-ead8bc86-5bc9-435e-a5f1-9d65aaa383fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974147274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 974147274 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.24431494 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 360599997 ps |
CPU time | 1.14 seconds |
Started | Jul 21 05:49:21 PM PDT 24 |
Finished | Jul 21 05:49:23 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-acbf2abb-cc8c-41ae-bbbc-8dc8e38c41a1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24431494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.24431494 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3100704519 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 4165975041 ps |
CPU time | 8.16 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:38 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-856c84c8-aa2b-41b8-8283-ec5570331872 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100704519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3100704519 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.744693119 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 28932123696 ps |
CPU time | 50.04 seconds |
Started | Jul 21 05:49:32 PM PDT 24 |
Finished | Jul 21 05:50:23 PM PDT 24 |
Peak memory | 221976 kb |
Host | smart-35bce860-55b0-4db4-881d-7f537f834c5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744693119 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.744693119 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.404683184 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 158155689 ps |
CPU time | 3.15 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:35 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-a00571e2-c281-4aea-9be1-38970c312f22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404683184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.404683184 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2235223882 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 5440959933 ps |
CPU time | 25.73 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:57 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-fc950033-d88c-4c8f-b7cc-0b266174a72b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235223882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2235223882 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1268346108 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 818099819 ps |
CPU time | 3.9 seconds |
Started | Jul 21 05:49:29 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 221724 kb |
Host | smart-bff815ec-7ef8-4fb3-95c8-bcfcfa0272da |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268346108 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1268346108 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1849929618 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 101546740 ps |
CPU time | 2.34 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:34 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-adb9fbf2-8813-426a-a1d0-713ba6c283e2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849929618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1849929618 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1432865106 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 9177691986 ps |
CPU time | 15.46 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:46 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-e10f8023-0af2-4f51-b031-da504b90cb11 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432865106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.1432865106 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.678743500 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 860811976 ps |
CPU time | 1.49 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-5f8a961e-5bc8-443b-b80e-1c516dd8be47 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678743500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.678743500 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2973957190 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 221301255 ps |
CPU time | 0.88 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-6ce2847a-4a49-488e-8430-d4c66593844b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973957190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2 973957190 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3232161603 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 960166316 ps |
CPU time | 3.5 seconds |
Started | Jul 21 05:49:28 PM PDT 24 |
Finished | Jul 21 05:49:32 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-6b10ed3e-2586-4cfc-a0ba-e6e652274f80 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232161603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3232161603 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2349262268 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 49869312105 ps |
CPU time | 76.75 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:50:49 PM PDT 24 |
Peak memory | 221964 kb |
Host | smart-1eccb5cb-21a3-487e-be17-f83efc1462fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349262268 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2349262268 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4028022703 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 366143263 ps |
CPU time | 2.13 seconds |
Started | Jul 21 05:49:33 PM PDT 24 |
Finished | Jul 21 05:49:35 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-3fe3a3f6-5813-4a2f-ab23-206b637d2620 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028022703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4028022703 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.5631669 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 6884816683 ps |
CPU time | 18.55 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:49 PM PDT 24 |
Peak memory | 213716 kb |
Host | smart-d942b1ef-1cc3-4bfd-afd4-554cd22a9ec2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5631669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.5631669 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.292472245 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 283095607 ps |
CPU time | 2.03 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:32 PM PDT 24 |
Peak memory | 215656 kb |
Host | smart-43435591-4e48-46cc-b8c8-98af1e5b13ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292472245 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.292472245 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1874358063 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 142682001 ps |
CPU time | 1.42 seconds |
Started | Jul 21 05:49:30 PM PDT 24 |
Finished | Jul 21 05:49:33 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-c560aed3-5985-4ec1-9f8c-e28f7bcbc13f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874358063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1874358063 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1564677367 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 59310528 ps |
CPU time | 0.77 seconds |
Started | Jul 21 05:49:28 PM PDT 24 |
Finished | Jul 21 05:49:29 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-12430493-51ab-4299-8207-5f426f140324 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564677367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.1564677367 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3688221532 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 3792754203 ps |
CPU time | 4.09 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:36 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-c1f39328-096a-48c9-b0e1-248add850084 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688221532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 688221532 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1640133917 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 794212272 ps |
CPU time | 1.76 seconds |
Started | Jul 21 05:49:29 PM PDT 24 |
Finished | Jul 21 05:49:31 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-d53d7f42-74a5-4f72-a655-fae0bbbed3fc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640133917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 640133917 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4287667067 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 616392485 ps |
CPU time | 6.46 seconds |
Started | Jul 21 05:49:29 PM PDT 24 |
Finished | Jul 21 05:49:36 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-1d8d4643-c425-4438-89a1-f30d6e8a09d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287667067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.4287667067 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.480502983 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 181162619548 ps |
CPU time | 251.27 seconds |
Started | Jul 21 05:49:32 PM PDT 24 |
Finished | Jul 21 05:53:44 PM PDT 24 |
Peak memory | 230776 kb |
Host | smart-7880b61d-4d45-4e11-89a8-82096926cdc5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480502983 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.480502983 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.181408086 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 81816895 ps |
CPU time | 4.34 seconds |
Started | Jul 21 05:49:31 PM PDT 24 |
Finished | Jul 21 05:49:37 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-c9ba382a-a586-40cd-bd14-f67d2d0ff854 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181408086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.181408086 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1510453142 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 4673560276 ps |
CPU time | 26.17 seconds |
Started | Jul 21 05:49:32 PM PDT 24 |
Finished | Jul 21 05:49:59 PM PDT 24 |
Peak memory | 213744 kb |
Host | smart-68b41689-5328-4fca-ab5d-b3c554dc6811 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510453142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1510453142 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2985596509 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 135904101 ps |
CPU time | 0.83 seconds |
Started | Jul 21 07:05:34 PM PDT 24 |
Finished | Jul 21 07:05:36 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-91e2b58a-5a23-4b15-a917-6532841057b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985596509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2985596509 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3293068931 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2767927334 ps |
CPU time | 3.85 seconds |
Started | Jul 21 07:05:40 PM PDT 24 |
Finished | Jul 21 07:05:46 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-3e18a9be-0491-4566-833a-61b9f05c57a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293068931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3293068931 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1060586926 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1634274793 ps |
CPU time | 3.76 seconds |
Started | Jul 21 07:05:36 PM PDT 24 |
Finished | Jul 21 07:05:41 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-b8571e8f-71ec-4c19-903a-fc9811b98ecb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060586926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1060586926 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.1620181528 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 614359259 ps |
CPU time | 1.11 seconds |
Started | Jul 21 07:05:38 PM PDT 24 |
Finished | Jul 21 07:05:41 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-6f322aa5-357f-43f9-80a1-91bbc9955e38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620181528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1620181528 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2924758281 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 199493749 ps |
CPU time | 0.82 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-ba9bd882-46c7-4530-9569-6f28f36bc714 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924758281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2924758281 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1124536686 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 187062529 ps |
CPU time | 1.12 seconds |
Started | Jul 21 07:05:40 PM PDT 24 |
Finished | Jul 21 07:05:43 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-7df34184-ab7f-4990-89a6-8264f4d0aece |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124536686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1124536686 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.2165820293 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 120442860 ps |
CPU time | 0.9 seconds |
Started | Jul 21 07:05:40 PM PDT 24 |
Finished | Jul 21 07:05:43 PM PDT 24 |
Peak memory | 215576 kb |
Host | smart-e79db776-b770-49d9-9103-6a4b7396cbe5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165820293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2165820293 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.250816590 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1555525697 ps |
CPU time | 5.12 seconds |
Started | Jul 21 07:05:39 PM PDT 24 |
Finished | Jul 21 07:05:46 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-9353df4c-15c8-4304-b1e4-23e116340a77 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=250816590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl _access.250816590 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.19357737 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 715808718 ps |
CPU time | 2.52 seconds |
Started | Jul 21 07:05:45 PM PDT 24 |
Finished | Jul 21 07:05:53 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-2921a07b-51eb-48f3-b001-b8c52840e0cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19357737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.19357737 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.343154474 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 898967770 ps |
CPU time | 3.19 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:48 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-84c8402c-5210-48a3-bd2c-9af5cd0880ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343154474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.343154474 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1125752920 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 410651182 ps |
CPU time | 1.3 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-f50266f8-da73-4aff-9212-43adb69f76ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125752920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1125752920 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.621120221 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 429815155 ps |
CPU time | 1.08 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-b636c885-7453-4c0d-8681-eebd1f49707b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621120221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.621120221 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3654513876 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1586016494 ps |
CPU time | 5.2 seconds |
Started | Jul 21 07:05:38 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-d80297fc-7253-4eac-8c82-668c85593262 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654513876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3654513876 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4059944803 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 333674694 ps |
CPU time | 0.9 seconds |
Started | Jul 21 07:05:37 PM PDT 24 |
Finished | Jul 21 07:05:39 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-fedad9b4-d076-40ff-aef6-e0201f2cb7c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059944803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4059944803 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.588842148 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 459860135 ps |
CPU time | 1.37 seconds |
Started | Jul 21 07:05:37 PM PDT 24 |
Finished | Jul 21 07:05:40 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-d0d5e40a-135f-404f-a8b9-e36b2b6cfc8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588842148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.588842148 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1003634263 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 2595058969 ps |
CPU time | 5.14 seconds |
Started | Jul 21 07:05:40 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-48a63739-04b4-4d16-8459-42d81e43f63d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003634263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1003634263 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.3830311056 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 131062470 ps |
CPU time | 0.77 seconds |
Started | Jul 21 07:05:37 PM PDT 24 |
Finished | Jul 21 07:05:40 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-aa97c976-f089-46f0-a611-a6d28da1f438 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830311056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3830311056 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.24710986 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 488362128 ps |
CPU time | 1.91 seconds |
Started | Jul 21 07:05:37 PM PDT 24 |
Finished | Jul 21 07:05:40 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-0c66df60-c6ce-4c83-82a6-64117282705a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24710986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.24710986 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.529337252 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 10633854581 ps |
CPU time | 4.28 seconds |
Started | Jul 21 07:05:40 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-fbe36115-3e77-4eef-9742-dc6a281d5101 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529337252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.529337252 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.3262200707 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1578647994 ps |
CPU time | 2.39 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:48 PM PDT 24 |
Peak memory | 229432 kb |
Host | smart-51f51530-daf2-457d-a228-f624c796c15c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262200707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3262200707 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.227385006 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1113250167 ps |
CPU time | 1.58 seconds |
Started | Jul 21 07:05:37 PM PDT 24 |
Finished | Jul 21 07:05:40 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-c4229c17-e866-482a-98f5-44fa63b49834 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227385006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.227385006 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1338303378 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 9407519996 ps |
CPU time | 11.12 seconds |
Started | Jul 21 07:05:38 PM PDT 24 |
Finished | Jul 21 07:05:51 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-7ff26f69-e251-48a6-966c-b98a3880eafa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338303378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1338303378 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.3333127189 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 96139621 ps |
CPU time | 0.96 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-c277e82a-47e9-48fc-a68b-99618ff86dfc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333127189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3333127189 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.3946361141 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 32533328 ps |
CPU time | 0.73 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:50 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-6f231869-2a16-48e9-8b79-c3b5c2ba2652 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946361141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3946361141 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1908255449 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 79130039209 ps |
CPU time | 226.35 seconds |
Started | Jul 21 07:05:43 PM PDT 24 |
Finished | Jul 21 07:09:31 PM PDT 24 |
Peak memory | 217672 kb |
Host | smart-cfabfbcf-127a-46ab-ae88-535231838aae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908255449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1908255449 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4005820956 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 1931984685 ps |
CPU time | 2.16 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:48 PM PDT 24 |
Peak memory | 221788 kb |
Host | smart-5e32618b-3cda-45b7-8e33-e70b0f5e93fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005820956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4005820956 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2532294427 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 197251030 ps |
CPU time | 1.12 seconds |
Started | Jul 21 07:05:40 PM PDT 24 |
Finished | Jul 21 07:05:43 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-3de5f096-836c-474e-b3a6-dd867b22d7eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532294427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2532294427 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.111252142 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 3248731227 ps |
CPU time | 3 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:46 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-3dd717b0-b3d2-4e3a-b542-1d07ce915cce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111252142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.111252142 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3742834019 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 1037794783 ps |
CPU time | 2.26 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-acefa587-2cc1-4f8b-a831-9b6c12a68a42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742834019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3742834019 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3458549900 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 497934235 ps |
CPU time | 1.42 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-00d15f9a-cfe1-49d6-863b-a2ad74a27a44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458549900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3458549900 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4195894002 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 164175009 ps |
CPU time | 0.74 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-c8b290a3-9459-42b3-8b04-a03fcf9f4d52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195894002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4195894002 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1084406609 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1523216092 ps |
CPU time | 3.2 seconds |
Started | Jul 21 07:05:39 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-00228968-77ff-40b7-8e31-12fa89e65299 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1084406609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.1084406609 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.3608396134 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 520289778 ps |
CPU time | 1.47 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-60fbf6c9-32bb-4429-8af5-5369ce1295c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608396134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3608396134 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1465594692 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 1725263443 ps |
CPU time | 5.41 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:50 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-63d9eb08-606d-4ec1-9c41-97926fea0106 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465594692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1465594692 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.856692358 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 476341969 ps |
CPU time | 1.07 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:05:56 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-3fc116d0-a08d-4d26-933d-2fecafde7773 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856692358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.856692358 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3067349650 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 787205585 ps |
CPU time | 1.47 seconds |
Started | Jul 21 07:05:43 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-6c544ec1-7fcf-4405-a536-92944b0a027a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067349650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3067349650 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.662321401 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 2926120437 ps |
CPU time | 3.43 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:49 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-db8b7ee4-6743-4e38-a9a1-209498d38906 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662321401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.662321401 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1576892683 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 545482336 ps |
CPU time | 1.08 seconds |
Started | Jul 21 07:05:43 PM PDT 24 |
Finished | Jul 21 07:05:46 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-3d0a87f1-e6ee-4e0e-8ee7-ff97ef135995 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576892683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1576892683 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2544693616 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 1226722135 ps |
CPU time | 3.48 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-238f4486-5c80-43ae-a439-f8e24424f5ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544693616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2544693616 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2397376548 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 2631513532 ps |
CPU time | 1.95 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-334eb06f-b780-4bf5-8473-fe23ff236731 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397376548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2397376548 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.4103027952 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 819013400 ps |
CPU time | 1.36 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-d4214c81-46c8-4f86-8aa3-9e9d8834dfa1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103027952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4103027952 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2052961924 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 346948174 ps |
CPU time | 1.1 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-f335aed9-beb8-4cca-a324-1a6893a79cd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052961924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2052961924 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.756300470 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 69443602 ps |
CPU time | 0.96 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:45 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-658d6a7b-d64f-4f9c-a480-77edfe3ea46f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756300470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.756300470 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1050920785 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 750537846 ps |
CPU time | 2.11 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:47 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-45171027-e229-491e-89a2-14dfa12cafd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050920785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1050920785 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.4228023873 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 3245623028 ps |
CPU time | 8.89 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:05:52 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-165d418e-c3f1-4d14-8b57-f866359b35a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228023873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4228023873 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.1420410115 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 2149428504 ps |
CPU time | 6.42 seconds |
Started | Jul 21 07:05:38 PM PDT 24 |
Finished | Jul 21 07:05:46 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-c16856bc-5492-4ffc-bb2d-e03c2baea3a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420410115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1420410115 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.3541727258 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 2043292420 ps |
CPU time | 2.32 seconds |
Started | Jul 21 07:05:44 PM PDT 24 |
Finished | Jul 21 07:05:48 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-bde9ffe9-a2da-4ef0-bdb9-90fe77afee7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541727258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3541727258 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1472263446 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 133848937 ps |
CPU time | 0.78 seconds |
Started | Jul 21 07:06:04 PM PDT 24 |
Finished | Jul 21 07:06:06 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-858b472e-d1e5-4602-8c1a-eb778ccf01c2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472263446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1472263446 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.500651579 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 14438571008 ps |
CPU time | 22.81 seconds |
Started | Jul 21 07:06:01 PM PDT 24 |
Finished | Jul 21 07:06:24 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-f2cd47f4-f0be-44dd-a393-dcc4fbf135c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500651579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.500651579 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3895794304 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 3528949980 ps |
CPU time | 2.79 seconds |
Started | Jul 21 07:06:03 PM PDT 24 |
Finished | Jul 21 07:06:06 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-a683ea75-7c8b-49cb-9d76-8994a26fd6fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895794304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3895794304 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.462307196 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1706640055 ps |
CPU time | 5.54 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:14 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-5c0a252e-e142-4fe4-a168-6aecc9b1c78c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=462307196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t l_access.462307196 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.4116779799 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 6665414120 ps |
CPU time | 18.82 seconds |
Started | Jul 21 07:05:58 PM PDT 24 |
Finished | Jul 21 07:06:17 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-418045b3-b1a0-4c45-b724-6cabc0d37f4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116779799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4116779799 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.2477834368 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 3728730516 ps |
CPU time | 4.13 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-b618d116-d7c4-45e4-99be-7dfc8777c801 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477834368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2477834368 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.3925163112 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 307981306 ps |
CPU time | 0.72 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-bc5e21b8-1e62-48c7-b847-5588d2aba3cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925163112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3925163112 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3322667098 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 8479985764 ps |
CPU time | 28.71 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:40 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-f0c660bc-6a6d-47c3-b359-4b0cc325c4c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322667098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3322667098 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2674192096 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 6572014885 ps |
CPU time | 5.14 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:16 PM PDT 24 |
Peak memory | 215012 kb |
Host | smart-78137f9d-5189-4480-a2d5-d5efcfab97a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674192096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2674192096 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3111915815 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 1630612717 ps |
CPU time | 3.22 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-37d22dbf-0e76-40db-b22c-b90c2cf8a98d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3111915815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3111915815 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.493568682 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 2023995814 ps |
CPU time | 3.21 seconds |
Started | Jul 21 07:06:01 PM PDT 24 |
Finished | Jul 21 07:06:04 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-b013b2ee-7866-4ea8-84f1-2dde3e4c2b00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493568682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.493568682 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.948825109 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 3953608973 ps |
CPU time | 2.96 seconds |
Started | Jul 21 07:06:02 PM PDT 24 |
Finished | Jul 21 07:06:05 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-0ccaea80-5738-41bd-a2af-3aee9a3f06b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948825109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.948825109 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.3758768231 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 31210689 ps |
CPU time | 0.77 seconds |
Started | Jul 21 07:06:22 PM PDT 24 |
Finished | Jul 21 07:06:24 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-61614428-19db-4397-9831-70f0333a1953 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758768231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3758768231 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.404644667 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 9506893232 ps |
CPU time | 7.9 seconds |
Started | Jul 21 07:06:16 PM PDT 24 |
Finished | Jul 21 07:06:24 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-5f7bd431-16ce-4106-bf35-2a475a234217 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404644667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.404644667 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2049221755 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 6030792950 ps |
CPU time | 5.98 seconds |
Started | Jul 21 07:06:05 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-67b0e782-060f-4870-9119-1f72533de33a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049221755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2049221755 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.697043063 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2639050569 ps |
CPU time | 8.45 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:17 PM PDT 24 |
Peak memory | 205540 kb |
Host | smart-cb9a30ee-bfdd-4950-ae54-31f2b12e70de |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=697043063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t l_access.697043063 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.864820742 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 1267485359 ps |
CPU time | 4.73 seconds |
Started | Jul 21 07:05:59 PM PDT 24 |
Finished | Jul 21 07:06:04 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-d41602aa-d9dd-4533-860a-2e70f4942ed4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864820742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.864820742 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.2237892350 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 3185922355 ps |
CPU time | 5.11 seconds |
Started | Jul 21 07:06:04 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-64411b22-3db1-447d-926f-071b90c817ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237892350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2237892350 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.2695797349 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 29552542 ps |
CPU time | 0.73 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:11 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-19da90a7-28d7-4234-bdeb-4d37a910a569 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695797349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2695797349 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2809632623 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 7623373106 ps |
CPU time | 12.65 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:39 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-74ddacfa-da01-4a6c-a852-b8ac098c0e76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809632623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2809632623 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3857211946 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1958606806 ps |
CPU time | 2.96 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-3e0dda39-3c65-4c63-b023-5183cdf772c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857211946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3857211946 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4123897990 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1315399776 ps |
CPU time | 4.79 seconds |
Started | Jul 21 07:06:13 PM PDT 24 |
Finished | Jul 21 07:06:18 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-137523d6-ba97-4cd1-808b-f4692a705116 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4123897990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.4123897990 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.1809822601 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 1078197451 ps |
CPU time | 2.55 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:29 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-86967e2c-7806-4ab9-94cc-0ee4cb9a1103 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809822601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1809822601 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.3030283583 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 10437253034 ps |
CPU time | 30.3 seconds |
Started | Jul 21 07:06:12 PM PDT 24 |
Finished | Jul 21 07:06:43 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-3e2380ba-749f-4155-b226-e3960334be6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030283583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3030283583 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.677981916 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 63604791 ps |
CPU time | 0.78 seconds |
Started | Jul 21 07:06:15 PM PDT 24 |
Finished | Jul 21 07:06:17 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-104f3c9c-c587-4cf1-8133-848b81c4fca0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677981916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.677981916 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1644422679 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 3016001666 ps |
CPU time | 3.04 seconds |
Started | Jul 21 07:06:07 PM PDT 24 |
Finished | Jul 21 07:06:10 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-8a81b11c-932a-4f3e-9d25-32deed983d43 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1644422679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.1644422679 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.236265002 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 2672867284 ps |
CPU time | 8.36 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-9f9b2f33-bd2e-4a51-b830-795ecda2e835 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236265002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.236265002 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1092988139 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 181771360 ps |
CPU time | 0.72 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-3b65865b-7846-4f3f-a293-3a08dc9a3e6b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092988139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1092988139 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.4011715446 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1641785401 ps |
CPU time | 2.31 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-9a0e8964-ff65-4613-acb4-c4632d5a9205 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011715446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.4011715446 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1293126902 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 8918500112 ps |
CPU time | 6.98 seconds |
Started | Jul 21 07:06:19 PM PDT 24 |
Finished | Jul 21 07:06:26 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-1ad0d577-36fd-47ff-9435-1684df28e9ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293126902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1293126902 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1922015297 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 2940069011 ps |
CPU time | 4.68 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:14 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-0bf66fc8-1a6d-4a11-8abc-48549bf2ec87 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1922015297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.1922015297 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.3502386388 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 8594845808 ps |
CPU time | 14.58 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:41 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-f1265a56-abf7-4379-8581-5105677f0d3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502386388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3502386388 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2002362771 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 29934927 ps |
CPU time | 0.71 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:10 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-3358a812-5afe-4880-a822-1507bf65d78b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002362771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2002362771 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.4069620725 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 36139980714 ps |
CPU time | 28.7 seconds |
Started | Jul 21 07:06:13 PM PDT 24 |
Finished | Jul 21 07:06:42 PM PDT 24 |
Peak memory | 213716 kb |
Host | smart-e72d894e-97d4-426e-a36f-74e8f1efa587 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4069620725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4069620725 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.270878327 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 1534705268 ps |
CPU time | 2.84 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-7309d471-4cef-4e05-873d-1b2d94da9037 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270878327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.270878327 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.234618012 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1274152796 ps |
CPU time | 1.89 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:10 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-165713cc-8286-4e7e-8ea2-da0fec3ffadd |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=234618012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t l_access.234618012 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1280396869 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 5265108837 ps |
CPU time | 3.1 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-d585e635-ec09-4c61-af89-bb0f4edd62c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280396869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1280396869 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.3678014441 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 9933367444 ps |
CPU time | 15.34 seconds |
Started | Jul 21 07:06:18 PM PDT 24 |
Finished | Jul 21 07:06:34 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-7b045b4f-d046-4267-92f6-1ee4a25684f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678014441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3678014441 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2913032069 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 37885864 ps |
CPU time | 0.79 seconds |
Started | Jul 21 07:06:23 PM PDT 24 |
Finished | Jul 21 07:06:25 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-997305a6-2c5a-4286-bb63-55c42baa1f55 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913032069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2913032069 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3662097577 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 23595625759 ps |
CPU time | 14.17 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:25 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-de5a5926-c657-4aa5-a3df-23623132aaa0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662097577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3662097577 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1228510773 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 8327905516 ps |
CPU time | 20.31 seconds |
Started | Jul 21 07:06:15 PM PDT 24 |
Finished | Jul 21 07:06:37 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-c4f2061e-adb1-4894-91b2-1fd50fffc82e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228510773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1228510773 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1866507192 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 5999968322 ps |
CPU time | 11.48 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:21 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-0034984b-1970-4873-850a-12783f7f5b05 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1866507192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.1866507192 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.1629727302 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 6482018151 ps |
CPU time | 10.39 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:22 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-54e49e7c-4b6b-4da3-b3eb-e76945ae38a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629727302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1629727302 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.3212901794 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 3531779478 ps |
CPU time | 3.69 seconds |
Started | Jul 21 07:06:19 PM PDT 24 |
Finished | Jul 21 07:06:23 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-6a49acb7-6a54-4a15-8780-ad8c96dbc253 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212901794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3212901794 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.222792629 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 42112134 ps |
CPU time | 0.73 seconds |
Started | Jul 21 07:06:27 PM PDT 24 |
Finished | Jul 21 07:06:30 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-280a4c26-469a-4918-9116-81d63ff1def8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222792629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.222792629 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.484953008 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 29788665234 ps |
CPU time | 16.74 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:29 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-66997c6d-80e0-46c8-b057-4f0be52224f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484953008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.484953008 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3916823969 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 8890117862 ps |
CPU time | 25.45 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:36 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-23520fec-d665-4c4c-b2ae-72e9e508dad9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916823969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3916823969 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3500133545 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 7169021049 ps |
CPU time | 5.23 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:16 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-99aa00c3-a3a9-4a5a-b8ea-fe2e8a77140b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3500133545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3500133545 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.4266812537 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 971819361 ps |
CPU time | 2.44 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:29 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-4b282543-1ca1-4041-b82a-245a03646438 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266812537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.4266812537 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.674784835 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 4858240502 ps |
CPU time | 7.05 seconds |
Started | Jul 21 07:06:25 PM PDT 24 |
Finished | Jul 21 07:06:35 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-48bbaee1-a091-4271-b424-f3ac1d3c70cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674784835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.674784835 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.4066693538 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 40206918 ps |
CPU time | 0.77 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:27 PM PDT 24 |
Peak memory | 204620 kb |
Host | smart-04c23f25-35a2-4fa4-9699-790f93fc5d37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066693538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.4066693538 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1525359789 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 2557178786 ps |
CPU time | 7.83 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:20 PM PDT 24 |
Peak memory | 214784 kb |
Host | smart-8b5bcbc1-375c-4f59-81d8-9f7164940322 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525359789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1525359789 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2605073039 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1141049759 ps |
CPU time | 3.17 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:29 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-02ac930a-ed48-4549-ba52-eeae090fca95 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2605073039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.2605073039 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.2087920199 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 2945095130 ps |
CPU time | 3.39 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:14 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-ff21ffc7-772a-4880-8780-3f3c6c295ee9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087920199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2087920199 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.1560106780 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 6137960599 ps |
CPU time | 5.75 seconds |
Started | Jul 21 07:06:23 PM PDT 24 |
Finished | Jul 21 07:06:31 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-810807b4-4947-40e1-9e0d-066993bee47e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560106780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1560106780 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2417136024 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 12884624807 ps |
CPU time | 17.11 seconds |
Started | Jul 21 07:05:41 PM PDT 24 |
Finished | Jul 21 07:06:00 PM PDT 24 |
Peak memory | 221844 kb |
Host | smart-446ee9fa-7aef-4053-9024-2e2810672902 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417136024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2417136024 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2089281327 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 4791539727 ps |
CPU time | 4.33 seconds |
Started | Jul 21 07:05:43 PM PDT 24 |
Finished | Jul 21 07:05:50 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-934aa32f-dc5a-4be1-8290-307dbf02f606 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089281327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2089281327 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.603663775 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 1613049332 ps |
CPU time | 5.38 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:06:00 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-df8927e6-9dc3-473b-b480-e3a4cd219812 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=603663775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl _access.603663775 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.1498111520 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 125764690 ps |
CPU time | 0.85 seconds |
Started | Jul 21 07:05:42 PM PDT 24 |
Finished | Jul 21 07:05:44 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-535e0491-087f-4b2e-be8b-11765653c5b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498111520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1498111520 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.739004682 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2452364894 ps |
CPU time | 2.37 seconds |
Started | Jul 21 07:05:52 PM PDT 24 |
Finished | Jul 21 07:05:54 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-313ad77e-33bd-4111-b44f-e3ba5815325c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739004682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.739004682 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2837673442 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 507451437 ps |
CPU time | 1.31 seconds |
Started | Jul 21 07:05:55 PM PDT 24 |
Finished | Jul 21 07:05:57 PM PDT 24 |
Peak memory | 229756 kb |
Host | smart-484b06a1-c7cb-487f-8888-5d0b81ba4314 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837673442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2837673442 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2969163082 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 102957423 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:27 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-b7ec825b-f575-4667-b82b-a960ceef30dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969163082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2969163082 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.958314036 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 68872212 ps |
CPU time | 0.85 seconds |
Started | Jul 21 07:06:17 PM PDT 24 |
Finished | Jul 21 07:06:19 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-7e2fad47-4b00-45c7-b460-52e7c7f05400 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958314036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.958314036 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.446881429 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 128373390 ps |
CPU time | 0.81 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:11 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-d05acc90-62c1-497c-9a06-16eeede010b2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446881429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.446881429 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.1453567778 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 7788946930 ps |
CPU time | 5.14 seconds |
Started | Jul 21 07:06:16 PM PDT 24 |
Finished | Jul 21 07:06:21 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-25affc0e-97b8-40e3-9ae2-2ca6bcc957d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453567778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1453567778 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3096275957 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 74071805 ps |
CPU time | 0.88 seconds |
Started | Jul 21 07:06:27 PM PDT 24 |
Finished | Jul 21 07:06:31 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-01eecc13-d158-4f01-a827-d350467e6e5b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096275957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3096275957 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.3348262020 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 7215758433 ps |
CPU time | 4.69 seconds |
Started | Jul 21 07:06:13 PM PDT 24 |
Finished | Jul 21 07:06:19 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-2c015e76-4bf7-4cac-9b83-81e0941660e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348262020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3348262020 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1729557624 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 63632935 ps |
CPU time | 0.74 seconds |
Started | Jul 21 07:06:11 PM PDT 24 |
Finished | Jul 21 07:06:13 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-f45f8dd7-1030-4695-908d-3376c479145e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729557624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1729557624 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.3313286773 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 82920489 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:06:18 PM PDT 24 |
Finished | Jul 21 07:06:20 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-cb7bb6b4-bb8e-456d-b2ec-26d9073b1f42 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313286773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3313286773 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.2659887329 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 7388398038 ps |
CPU time | 5 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-fefcd05d-495f-4bae-aa80-ab73e41085ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659887329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2659887329 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2700907024 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 262449123 ps |
CPU time | 0.74 seconds |
Started | Jul 21 07:06:25 PM PDT 24 |
Finished | Jul 21 07:06:28 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-b6024a99-cec5-43e8-b777-d864a6634fdd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700907024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2700907024 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.2571843791 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 5216563726 ps |
CPU time | 14.78 seconds |
Started | Jul 21 07:06:13 PM PDT 24 |
Finished | Jul 21 07:06:28 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-e1152a2a-2556-438b-a86e-a0a4d91b3213 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571843791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2571843791 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.1730085872 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 123265772 ps |
CPU time | 0.99 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-55dcc59d-d2a2-47ae-ae65-33a708a24909 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730085872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1730085872 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.1849986843 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 55743627 ps |
CPU time | 0.69 seconds |
Started | Jul 21 07:06:15 PM PDT 24 |
Finished | Jul 21 07:06:16 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-d6e7fad5-608b-4565-a49e-3d8a14e3a0ce |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849986843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1849986843 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.3275022742 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 5308231909 ps |
CPU time | 15.8 seconds |
Started | Jul 21 07:06:16 PM PDT 24 |
Finished | Jul 21 07:06:32 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-1ec51e50-2f71-4d21-bea9-19bee870096b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275022742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3275022742 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.1970904109 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 145223739 ps |
CPU time | 0.74 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:11 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-0c49255b-741a-4012-a205-bc61f64cf626 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970904109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1970904109 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.2164094091 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 33791834 ps |
CPU time | 0.76 seconds |
Started | Jul 21 07:05:52 PM PDT 24 |
Finished | Jul 21 07:05:53 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-d5552100-d8d9-4725-98b0-f2c56d50cfc1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164094091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2164094091 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1285751884 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 50639334917 ps |
CPU time | 56.49 seconds |
Started | Jul 21 07:06:03 PM PDT 24 |
Finished | Jul 21 07:07:00 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-a8401a67-7a45-494d-b608-3c24ddd5dee8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285751884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1285751884 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.901766820 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 15731458526 ps |
CPU time | 17.93 seconds |
Started | Jul 21 07:05:53 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 221876 kb |
Host | smart-38c8d015-1919-4b19-9881-2056712b340e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901766820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.901766820 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4134183283 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 9473562489 ps |
CPU time | 8.99 seconds |
Started | Jul 21 07:06:03 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-c00b2618-505c-4e51-99aa-3aa3648f0095 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4134183283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.4134183283 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.1050960701 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 110529145 ps |
CPU time | 0.82 seconds |
Started | Jul 21 07:05:53 PM PDT 24 |
Finished | Jul 21 07:05:54 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-5aac1902-7871-4efc-93b5-6bd3d9fd22b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050960701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1050960701 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3392586734 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 759709978 ps |
CPU time | 1.21 seconds |
Started | Jul 21 07:05:55 PM PDT 24 |
Finished | Jul 21 07:05:57 PM PDT 24 |
Peak memory | 228332 kb |
Host | smart-9d1b27fe-87f9-4bf0-ae20-bd86de5c0600 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392586734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3392586734 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3247484588 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 5183510760 ps |
CPU time | 15.16 seconds |
Started | Jul 21 07:05:47 PM PDT 24 |
Finished | Jul 21 07:06:03 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-8b568d9e-8994-4d15-8826-e74e371b2b28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247484588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3247484588 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.2808797431 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 57655903 ps |
CPU time | 0.85 seconds |
Started | Jul 21 07:06:27 PM PDT 24 |
Finished | Jul 21 07:06:31 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-bc59409a-93ef-4398-9497-3d5a8338c025 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808797431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2808797431 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.4290731831 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 56258531 ps |
CPU time | 0.72 seconds |
Started | Jul 21 07:06:25 PM PDT 24 |
Finished | Jul 21 07:06:28 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-63ae394e-0084-4cf4-976a-f302b98a1b3f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290731831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.4290731831 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.2226375288 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 142367377 ps |
CPU time | 0.84 seconds |
Started | Jul 21 07:06:25 PM PDT 24 |
Finished | Jul 21 07:06:28 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-b3cd81cb-e4b8-459a-903e-92d660485c7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226375288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2226375288 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.3060775087 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 58951687 ps |
CPU time | 0.73 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-c448994e-0780-4d28-83ae-9e11532da946 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060775087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3060775087 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.709811697 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 134085007 ps |
CPU time | 0.72 seconds |
Started | Jul 21 07:06:12 PM PDT 24 |
Finished | Jul 21 07:06:13 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-7a94d399-eaa7-4940-95c4-520598f2a034 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709811697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.709811697 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1926320692 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 69862820 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:06:18 PM PDT 24 |
Finished | Jul 21 07:06:20 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-ca975d3b-b45b-4b69-9965-31362282b8e7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926320692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1926320692 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.2268403658 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 3449979443 ps |
CPU time | 3.3 seconds |
Started | Jul 21 07:06:13 PM PDT 24 |
Finished | Jul 21 07:06:17 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-37a74d13-ee2b-48c9-822c-1f2b6b167ef8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268403658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2268403658 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.1164885276 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 115273533 ps |
CPU time | 0.72 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-166cccf1-b8f5-40c5-b8f8-8a0948933ce8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164885276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1164885276 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.1492421577 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2992767521 ps |
CPU time | 3.11 seconds |
Started | Jul 21 07:06:21 PM PDT 24 |
Finished | Jul 21 07:06:25 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-b2ea3eba-c4dc-490c-b5ed-8e8d457e1428 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492421577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1492421577 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.1073786602 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 50316636 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:06:16 PM PDT 24 |
Finished | Jul 21 07:06:18 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-a1757c98-26a8-4a24-8e15-b0825606fd0a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073786602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1073786602 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1212129522 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 87299027 ps |
CPU time | 0.8 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:16 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-a0672c3f-1ea9-41bd-9220-1ea2a0b5a4cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212129522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1212129522 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.279510722 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 2565716810 ps |
CPU time | 1.47 seconds |
Started | Jul 21 07:06:15 PM PDT 24 |
Finished | Jul 21 07:06:17 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-9aaae245-a475-4f96-a2b6-16c9ce2b7aa0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279510722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.279510722 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.2483975956 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 35186772 ps |
CPU time | 0.76 seconds |
Started | Jul 21 07:06:23 PM PDT 24 |
Finished | Jul 21 07:06:25 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-cf59d1f9-997e-4a18-b99e-a735c5c4e83c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483975956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2483975956 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.4194813482 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 11106671247 ps |
CPU time | 9.95 seconds |
Started | Jul 21 07:06:21 PM PDT 24 |
Finished | Jul 21 07:06:32 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-54e814c9-99c5-49cb-88e1-3698e7d22f6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194813482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.4194813482 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.21730646 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 71038446 ps |
CPU time | 0.77 seconds |
Started | Jul 21 07:05:52 PM PDT 24 |
Finished | Jul 21 07:05:54 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-a3393fe6-c366-48e3-a765-35fcb65006bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21730646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.21730646 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3420809924 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 65991319193 ps |
CPU time | 88.94 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:07:24 PM PDT 24 |
Peak memory | 214084 kb |
Host | smart-d5d96005-a6f5-4450-a94d-731af4e4517b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420809924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3420809924 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3146679796 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 7233086691 ps |
CPU time | 4.22 seconds |
Started | Jul 21 07:05:53 PM PDT 24 |
Finished | Jul 21 07:05:58 PM PDT 24 |
Peak memory | 221824 kb |
Host | smart-d39b2933-8954-4b9b-8a92-9e4e121f11ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146679796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3146679796 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3166888456 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1420554739 ps |
CPU time | 1.27 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:05:56 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-e94f0218-2ce9-4fbb-bb18-7d10831d2fe3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3166888456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3166888456 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1465716195 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 496438080 ps |
CPU time | 2.03 seconds |
Started | Jul 21 07:05:55 PM PDT 24 |
Finished | Jul 21 07:05:58 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-88d21666-010e-484c-880f-6c7c68e76985 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465716195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1465716195 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.1688298402 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 582257747 ps |
CPU time | 1.8 seconds |
Started | Jul 21 07:05:52 PM PDT 24 |
Finished | Jul 21 07:05:54 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-93b0aeb4-e180-4f17-a953-6609b17daaa6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688298402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1688298402 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.663047627 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 2966239614 ps |
CPU time | 5.12 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:06:00 PM PDT 24 |
Peak memory | 229716 kb |
Host | smart-8d0662be-7b4a-4c79-818e-e864b5a8f9c9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663047627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.663047627 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.477203875 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 10074066608 ps |
CPU time | 27.63 seconds |
Started | Jul 21 07:05:53 PM PDT 24 |
Finished | Jul 21 07:06:21 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-fe1eda80-eeee-49f3-9610-3af10e276b37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477203875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.477203875 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.4055494678 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 48985137 ps |
CPU time | 0.81 seconds |
Started | Jul 21 07:06:23 PM PDT 24 |
Finished | Jul 21 07:06:26 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-23dc74ce-aec6-4c44-acaa-3f45290bdc1b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055494678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4055494678 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.430486725 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1557739050 ps |
CPU time | 5 seconds |
Started | Jul 21 07:06:15 PM PDT 24 |
Finished | Jul 21 07:06:21 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-3a40694b-ad2c-40c9-a83a-46c19c12f0c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430486725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.430486725 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.259134615 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 113022914 ps |
CPU time | 0.81 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-40a95310-d406-455d-b97b-82abc4b650fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259134615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.259134615 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.1351459524 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 10598369654 ps |
CPU time | 11.29 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:38 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-974d8362-aecc-4fd8-842f-9b65867d1ca7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351459524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1351459524 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.1243022825 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 48634478 ps |
CPU time | 0.76 seconds |
Started | Jul 21 07:06:26 PM PDT 24 |
Finished | Jul 21 07:06:29 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-aa449f2d-19c2-4931-857a-a6283dcfdc16 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243022825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1243022825 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.2701568581 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 5519277522 ps |
CPU time | 3.53 seconds |
Started | Jul 21 07:06:16 PM PDT 24 |
Finished | Jul 21 07:06:20 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-b9cea799-47dc-441f-8879-a0c1cdda813d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701568581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2701568581 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.3537551790 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 250091414 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:06:21 PM PDT 24 |
Finished | Jul 21 07:06:22 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-3f242126-32f5-4b35-b8a5-3e001757600f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537551790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3537551790 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.1504319338 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 54062413 ps |
CPU time | 0.72 seconds |
Started | Jul 21 07:06:22 PM PDT 24 |
Finished | Jul 21 07:06:24 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-99a60adf-1be9-47e5-9e55-0dfe68eb70d3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504319338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1504319338 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.647015151 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 6060045682 ps |
CPU time | 2.37 seconds |
Started | Jul 21 07:06:26 PM PDT 24 |
Finished | Jul 21 07:06:31 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-30e8e334-0891-45db-ac20-22787202cd8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647015151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.647015151 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3841037545 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 90639470 ps |
CPU time | 0.75 seconds |
Started | Jul 21 07:06:14 PM PDT 24 |
Finished | Jul 21 07:06:16 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-c6eb61ee-77aa-436e-9f9b-d13d411e213b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841037545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3841037545 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.4226579797 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 42987149 ps |
CPU time | 0.83 seconds |
Started | Jul 21 07:06:27 PM PDT 24 |
Finished | Jul 21 07:06:31 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-dd49a78b-9f78-4c18-b0c0-ceac0847a5fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226579797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.4226579797 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.500221524 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 37494702 ps |
CPU time | 0.8 seconds |
Started | Jul 21 07:06:22 PM PDT 24 |
Finished | Jul 21 07:06:24 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-1e1f6f48-5365-41d4-98d4-4b1bc130cf91 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500221524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.500221524 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.1037617932 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 8495083034 ps |
CPU time | 5.85 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:33 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-cf078b10-40ad-47a5-8fad-8336b6697972 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037617932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1037617932 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.922961352 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 98736025 ps |
CPU time | 0.97 seconds |
Started | Jul 21 07:06:28 PM PDT 24 |
Finished | Jul 21 07:06:32 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-09bbf9cd-e656-4034-9aa9-ecb4c870c793 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922961352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.922961352 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2506240714 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 13244834419 ps |
CPU time | 11.03 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:37 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-0794a8ec-367c-48a6-97e1-3e9bbc404f66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506240714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2506240714 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.270558210 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 43185645 ps |
CPU time | 0.73 seconds |
Started | Jul 21 07:06:24 PM PDT 24 |
Finished | Jul 21 07:06:27 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-8f99bec2-ddf4-4a1c-af5b-4126d1e98701 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270558210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.270558210 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.378841971 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 4044978367 ps |
CPU time | 6.22 seconds |
Started | Jul 21 07:06:15 PM PDT 24 |
Finished | Jul 21 07:06:22 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-2c50afe6-e1a8-4c54-8874-49a5c7e1427d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378841971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.378841971 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.3433452383 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 86952801 ps |
CPU time | 0.82 seconds |
Started | Jul 21 07:06:05 PM PDT 24 |
Finished | Jul 21 07:06:06 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-0efbfd59-585b-435c-92e2-699c473138cc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433452383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3433452383 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3714644168 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 42888499659 ps |
CPU time | 127.73 seconds |
Started | Jul 21 07:05:49 PM PDT 24 |
Finished | Jul 21 07:07:57 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-3eb065ff-284c-42a4-895f-dde4545f4d13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714644168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3714644168 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.732072470 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2797378077 ps |
CPU time | 3.96 seconds |
Started | Jul 21 07:05:50 PM PDT 24 |
Finished | Jul 21 07:05:55 PM PDT 24 |
Peak memory | 205452 kb |
Host | smart-edf695e6-8499-4e86-89a9-04d1ed8d6869 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732072470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.732072470 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1049542602 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 1771667016 ps |
CPU time | 3.8 seconds |
Started | Jul 21 07:05:47 PM PDT 24 |
Finished | Jul 21 07:05:51 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-f6ff2dcc-e9f7-4bb0-b8cc-241c12ef6ae3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1049542602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.1049542602 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.3474811965 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 3686504360 ps |
CPU time | 7.02 seconds |
Started | Jul 21 07:05:49 PM PDT 24 |
Finished | Jul 21 07:05:56 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-f77de06d-f370-4a22-8047-76de0b93a93b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474811965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3474811965 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.946606701 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 61676879 ps |
CPU time | 0.76 seconds |
Started | Jul 21 07:05:55 PM PDT 24 |
Finished | Jul 21 07:05:56 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-b29aa6d3-67c5-4c07-a894-252fc3a8bc70 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946606701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.946606701 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4001940544 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 4443109099 ps |
CPU time | 5.32 seconds |
Started | Jul 21 07:06:09 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 214700 kb |
Host | smart-819cff0e-ee1a-4f46-b3b3-c4a24de555bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001940544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4001940544 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2752971585 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 3887342418 ps |
CPU time | 6.91 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:15 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-c7afe41c-58ab-48d1-abc9-afcf0052f4da |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2752971585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.2752971585 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.4218399477 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1890182794 ps |
CPU time | 2.42 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-f231b8f2-c20c-4932-91d9-6a3ac33ffc5a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218399477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.4218399477 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.2682996189 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 5680267739 ps |
CPU time | 17.15 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-0080dc42-b27d-4725-800f-f83f533ee377 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682996189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2682996189 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.2769034240 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 82558000 ps |
CPU time | 0.73 seconds |
Started | Jul 21 07:06:08 PM PDT 24 |
Finished | Jul 21 07:06:09 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-0251ec63-8a44-485d-b1e0-0804855b2ff0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769034240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2769034240 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3849329410 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 64911808243 ps |
CPU time | 19.61 seconds |
Started | Jul 21 07:05:58 PM PDT 24 |
Finished | Jul 21 07:06:18 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-1fa92ef1-3108-43e6-8832-407ea2b2c77f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849329410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3849329410 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1640323561 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1756764529 ps |
CPU time | 5.42 seconds |
Started | Jul 21 07:05:56 PM PDT 24 |
Finished | Jul 21 07:06:01 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-aeef3946-7292-4da8-a128-1abafa0699f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640323561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1640323561 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.583413119 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2428493669 ps |
CPU time | 7.51 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:06:03 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-3b483ec6-bd3e-47c3-9d7e-7f1cce358f15 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=583413119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl _access.583413119 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.1207033090 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 4345269527 ps |
CPU time | 7.66 seconds |
Started | Jul 21 07:05:53 PM PDT 24 |
Finished | Jul 21 07:06:01 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-c755a834-96b4-46ef-8dd7-bc36d52df00a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207033090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1207033090 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.2999759869 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 9678081803 ps |
CPU time | 11.49 seconds |
Started | Jul 21 07:05:53 PM PDT 24 |
Finished | Jul 21 07:06:06 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-11b29fa2-1c23-4c6a-8831-8245d9512543 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999759869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2999759869 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.430561093 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 39147432 ps |
CPU time | 0.78 seconds |
Started | Jul 21 07:06:04 PM PDT 24 |
Finished | Jul 21 07:06:05 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-8d35c587-63af-4771-a9a1-39f5e3fda4ec |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430561093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.430561093 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2704225495 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 5088397792 ps |
CPU time | 4.66 seconds |
Started | Jul 21 07:06:05 PM PDT 24 |
Finished | Jul 21 07:06:10 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-a4c471bc-77fe-4433-8ad7-5de82e339474 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704225495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2704225495 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3899291568 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 6325065100 ps |
CPU time | 6.53 seconds |
Started | Jul 21 07:06:05 PM PDT 24 |
Finished | Jul 21 07:06:12 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-9cf15dca-2909-4c0d-8195-ea2d52e29a35 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3899291568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.3899291568 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.3033169151 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 2716436694 ps |
CPU time | 5.03 seconds |
Started | Jul 21 07:05:54 PM PDT 24 |
Finished | Jul 21 07:06:00 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-493b7f75-09fa-4ed2-953e-f7e0f658cd04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033169151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3033169151 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.173508285 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 8510971523 ps |
CPU time | 23.89 seconds |
Started | Jul 21 07:05:56 PM PDT 24 |
Finished | Jul 21 07:06:20 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-5545f300-7555-4255-ba79-840f3d15911e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173508285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.173508285 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.806371388 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 107941724 ps |
CPU time | 0.93 seconds |
Started | Jul 21 07:06:00 PM PDT 24 |
Finished | Jul 21 07:06:01 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-7d9059cd-aeff-4828-a910-f1c44001b860 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806371388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.806371388 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3987983612 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 35484290989 ps |
CPU time | 31.05 seconds |
Started | Jul 21 07:06:06 PM PDT 24 |
Finished | Jul 21 07:06:37 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-1921c235-af60-48bb-99ea-45a60909e634 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987983612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3987983612 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.583959848 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1663566094 ps |
CPU time | 1.69 seconds |
Started | Jul 21 07:06:10 PM PDT 24 |
Finished | Jul 21 07:06:13 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-0c18bbf6-c67a-449b-9717-17507aebbe27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583959848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.583959848 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3967768647 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 3022575567 ps |
CPU time | 3.6 seconds |
Started | Jul 21 07:06:01 PM PDT 24 |
Finished | Jul 21 07:06:04 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-b081fe76-7e4f-4a92-9357-04d5f7167b1f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3967768647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.3967768647 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.2714739573 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 3935266515 ps |
CPU time | 4.97 seconds |
Started | Jul 21 07:06:05 PM PDT 24 |
Finished | Jul 21 07:06:11 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-b625fa56-4bb1-48ca-acae-8e099b98ebea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714739573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2714739573 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |