Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.19 95.77 81.52 89.91 75.00 86.50 98.53 55.12


Total tests in report: 443
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.38 61.38 87.68 87.68 60.55 60.55 60.34 60.34 52.50 52.50 69.17 69.17 93.48 93.48 5.92 5.92 /workspace/coverage/default/27.rv_dm_stress_all.1430800848
67.81 6.44 91.20 3.52 66.07 5.52 78.22 17.88 62.50 10.00 74.83 5.67 94.95 1.47 6.91 0.99 /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.85083787
73.50 5.69 91.30 0.10 69.79 3.72 78.96 0.74 62.50 0.00 75.50 0.67 96.00 1.05 40.44 33.54 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2647779620
75.63 2.13 91.35 0.05 70.21 0.41 80.72 1.76 70.00 7.50 76.00 0.50 96.00 0.00 45.13 4.69 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2855777668
77.07 1.44 92.00 0.65 72.28 2.07 82.81 2.09 73.75 3.75 77.50 1.50 96.00 0.00 45.13 0.00 /workspace/coverage/default/46.rv_dm_stress_all.1045578324
78.04 0.97 92.10 0.10 74.07 1.79 83.63 0.82 73.75 0.00 78.17 0.67 96.21 0.21 48.34 3.21 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.739631424
78.75 0.71 92.25 0.15 74.34 0.28 87.57 3.94 73.75 0.00 78.67 0.50 96.21 0.00 48.46 0.12 /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3471293295
79.45 0.70 92.71 0.45 75.31 0.97 87.57 0.00 75.00 1.25 80.50 1.83 96.21 0.00 48.83 0.37 /workspace/coverage/default/5.rv_dm_stress_all.328215194
79.99 0.54 93.16 0.45 76.69 1.38 88.47 0.90 75.00 0.00 81.17 0.67 96.21 0.00 49.20 0.37 /workspace/coverage/default/2.rv_dm_alert_test.2466527509
80.38 0.39 93.16 0.00 76.69 0.00 88.76 0.29 75.00 0.00 81.17 0.00 97.79 1.58 50.06 0.86 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1436251806
80.67 0.29 93.66 0.50 77.38 0.69 88.76 0.00 75.00 0.00 82.00 0.83 97.79 0.00 50.06 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.3604728364
80.90 0.24 93.71 0.05 78.07 0.69 88.76 0.00 75.00 0.00 82.17 0.17 97.79 0.00 50.80 0.74 /workspace/coverage/default/30.rv_dm_stress_all.1591490433
81.10 0.20 94.06 0.35 78.34 0.28 88.80 0.04 75.00 0.00 82.50 0.33 97.79 0.00 51.17 0.37 /workspace/coverage/default/37.rv_dm_stress_all.143918254
81.28 0.18 94.37 0.30 78.76 0.41 88.84 0.04 75.00 0.00 83.00 0.50 97.79 0.00 51.17 0.00 /workspace/coverage/default/1.rv_dm_debug_disabled.3533617941
81.45 0.17 94.67 0.30 79.17 0.41 88.84 0.00 75.00 0.00 83.50 0.50 97.79 0.00 51.17 0.00 /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1136297688
81.60 0.15 94.67 0.00 79.72 0.55 89.01 0.16 75.00 0.00 83.50 0.00 97.90 0.11 51.42 0.25 /workspace/coverage/default/1.rv_dm_sec_cm.677512238
81.73 0.13 94.72 0.05 80.28 0.55 89.01 0.00 75.00 0.00 83.67 0.17 97.90 0.00 51.54 0.12 /workspace/coverage/default/0.rv_dm_dmi_failed_op.219661315
81.86 0.13 95.02 0.30 80.28 0.00 89.09 0.08 75.00 0.00 84.17 0.50 97.90 0.00 51.54 0.00 /workspace/coverage/default/0.rv_dm_abstractcmd_status.4191681049
81.98 0.12 95.17 0.15 80.41 0.14 89.13 0.04 75.00 0.00 84.33 0.17 97.90 0.00 51.91 0.37 /workspace/coverage/default/9.rv_dm_stress_all.4087366132
82.09 0.11 95.17 0.00 80.55 0.14 89.29 0.16 75.00 0.00 84.83 0.50 97.90 0.00 51.91 0.00 /workspace/coverage/default/3.rv_dm_sba_tl_access.1778700949
82.20 0.11 95.27 0.10 80.69 0.14 89.29 0.00 75.00 0.00 85.33 0.50 97.90 0.00 51.91 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.2590098346
82.29 0.09 95.27 0.00 80.69 0.00 89.29 0.00 75.00 0.00 85.33 0.00 97.90 0.00 52.53 0.62 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1628446635
82.38 0.09 95.27 0.00 80.69 0.00 89.29 0.00 75.00 0.00 85.33 0.00 97.90 0.00 53.14 0.62 /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3765858802
82.46 0.08 95.42 0.15 80.83 0.14 89.29 0.00 75.00 0.00 85.50 0.17 97.90 0.00 53.27 0.12 /workspace/coverage/default/34.rv_dm_stress_all.1307101164
82.53 0.07 95.42 0.00 80.83 0.00 89.29 0.00 75.00 0.00 85.50 0.00 97.90 0.00 53.76 0.49 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4183114494
82.59 0.07 95.57 0.15 80.97 0.14 89.29 0.00 75.00 0.00 85.67 0.17 97.90 0.00 53.76 0.00 /workspace/coverage/default/21.rv_dm_stress_all.39777970
82.66 0.06 95.57 0.00 81.24 0.28 89.29 0.00 75.00 0.00 85.83 0.17 97.90 0.00 53.76 0.00 /workspace/coverage/default/1.rv_dm_progbuf_busy.2242701800
82.72 0.06 95.67 0.10 81.24 0.00 89.29 0.00 75.00 0.00 86.17 0.33 97.90 0.00 53.76 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2213769100
82.78 0.06 95.67 0.00 81.24 0.00 89.46 0.16 75.00 0.00 86.17 0.00 97.90 0.00 54.01 0.25 /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2112841357
82.83 0.05 95.67 0.00 81.24 0.00 89.46 0.00 75.00 0.00 86.17 0.00 97.90 0.00 54.38 0.37 /workspace/coverage/default/33.rv_dm_stress_all.2037134459
82.88 0.05 95.72 0.05 81.38 0.14 89.46 0.00 75.00 0.00 86.33 0.17 97.90 0.00 54.38 0.00 /workspace/coverage/default/0.rv_dm_hartsel_warl.934888774
82.92 0.04 95.72 0.00 81.38 0.00 89.54 0.08 75.00 0.00 86.33 0.00 98.11 0.21 54.38 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1673440561
82.96 0.04 95.72 0.00 81.38 0.00 89.70 0.16 75.00 0.00 86.33 0.00 98.11 0.00 54.50 0.12 /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.781429088
83.00 0.04 95.72 0.00 81.38 0.00 89.75 0.04 75.00 0.00 86.33 0.00 98.32 0.21 54.50 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4227334163
83.04 0.04 95.72 0.00 81.38 0.00 89.75 0.00 75.00 0.00 86.33 0.00 98.32 0.00 54.75 0.25 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.145941142
83.07 0.03 95.77 0.05 81.38 0.00 89.75 0.00 75.00 0.00 86.50 0.17 98.32 0.00 54.75 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.293455872
83.10 0.03 95.77 0.00 81.38 0.00 89.75 0.00 75.00 0.00 86.50 0.00 98.53 0.21 54.75 0.00 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.674674149
83.12 0.02 95.77 0.00 81.38 0.00 89.91 0.16 75.00 0.00 86.50 0.00 98.53 0.00 54.75 0.00 /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2231247727
83.14 0.02 95.77 0.00 81.52 0.14 89.91 0.00 75.00 0.00 86.50 0.00 98.53 0.00 54.75 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3588474299
83.16 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.53 0.00 54.87 0.12 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2283687103
83.17 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.53 0.00 54.99 0.12 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.515683668
83.19 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.53 0.00 55.12 0.12 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2605850750


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3053697503
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.36251384
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3743251756
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4272408191
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3317984903
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1671337440
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1610890876
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2346412971
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.763616679
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1548836793
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2798793132
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1163991451
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1913088939
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.413089219
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1190121714
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.666856044
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1372380564
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1910800142
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3129404881
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3248930403
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2046671743
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.556336122
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2335897373
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4154549493
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.803404237
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1382977005
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3122269985
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4105233193
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3765402907
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2426524072
/workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.196550859
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3332062493
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2888847493
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3610337895
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2450362229
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3524189255
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1341243799
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3255893119
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2554327643
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3267165257
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1776930702
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.332786926
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.308296740
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.207489564
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3953647691
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1379925300
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.965834475
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.81523140
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3004850750
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.183651725
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.476317363
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1150588284
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3505521794
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1145954937
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2180902402
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2173066649
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.906246963
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3818104252
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3793189522
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.569938947
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1617445481
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2479448937
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.793259927
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2027377024
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3542614527
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1571151714
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3776881174
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2924667297
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.468039952
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.978652384
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1541602855
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.492613790
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2865556143
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1149421846
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3527728140
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2673740013
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.645805373
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.299778556
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.638762519
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2755138699
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.395797251
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1721725240
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.307175572
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1759434269
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2541332696
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2398407669
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.957343694
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1795426349
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3121632609
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2543396637
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1755058450
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2139206948
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.262905237
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.599535569
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2298685782
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.50923271
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1525965830
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.247636315
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2862761108
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2300986896
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3705713533
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1854610082
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1801091046
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2353100213
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1413340420
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.299714644
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3677212783
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2741426456
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4154925691
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3374880372
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.409168305
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.599696958
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3623452969
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2493907010
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.871031351
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1199271007
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.37380839
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3148813866
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3934541125
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1746976355
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1176569943
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4286810688
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2949875209
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1427650991
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2902097792
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2917923659
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3171230751
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.949294763
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3794779467
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3497962306
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3300659918
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2732525641
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2836040242
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1918556552
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.487968566
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.880472716
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3836754115
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.590048920
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2848600198
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Total test records in report: 443
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/38.rv_dm_stress_all.279510722 Jul 21 07:06:15 PM PDT 24 Jul 21 07:06:17 PM PDT 24 2565716810 ps
T2 /workspace/coverage/default/0.rv_dm_ndmreset_req.3830311056 Jul 21 07:05:37 PM PDT 24 Jul 21 07:05:40 PM PDT 24 131062470 ps
T3 /workspace/coverage/default/46.rv_dm_stress_all.1045578324 Jul 21 07:06:20 PM PDT 24 Jul 21 07:06:23 PM PDT 24 1649166652 ps
T4 /workspace/coverage/default/27.rv_dm_stress_all.1430800848 Jul 21 07:06:18 PM PDT 24 Jul 21 07:06:23 PM PDT 24 3248421905 ps
T36 /workspace/coverage/default/2.rv_dm_alert_test.2466527509 Jul 21 07:05:49 PM PDT 24 Jul 21 07:05:56 PM PDT 24 38605000 ps
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T149 /workspace/coverage/default/0.rv_dm_sba_tl_access.529337252 Jul 21 07:05:40 PM PDT 24 Jul 21 07:05:47 PM PDT 24 10633854581 ps
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T206 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3322667098 Jul 21 07:06:10 PM PDT 24 Jul 21 07:06:40 PM PDT 24 8479985764 ps
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T33 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3588474299 Jul 21 07:05:41 PM PDT 24 Jul 21 07:05:44 PM PDT 24 345683733 ps
T187 /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2674192096 Jul 21 07:06:10 PM PDT 24 Jul 21 07:06:16 PM PDT 24 6572014885 ps
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T191 /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.500651579 Jul 21 07:06:01 PM PDT 24 Jul 21 07:06:24 PM PDT 24 14438571008 ps
T275 /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1293126902 Jul 21 07:06:19 PM PDT 24 Jul 21 07:06:26 PM PDT 24 8918500112 ps
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T178 /workspace/coverage/default/36.rv_dm_alert_test.1164885276 Jul 21 07:06:14 PM PDT 24 Jul 21 07:06:15 PM PDT 24 115273533 ps
T140 /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.484953008 Jul 21 07:06:11 PM PDT 24 Jul 21 07:06:29 PM PDT 24 29788665234 ps
T276 /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3662097577 Jul 21 07:06:10 PM PDT 24 Jul 21 07:06:25 PM PDT 24 23595625759 ps
T35 /workspace/coverage/default/0.rv_dm_rom_read_access.2590098346 Jul 21 07:05:36 PM PDT 24 Jul 21 07:05:39 PM PDT 24 97987126 ps
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T280 /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3166888456 Jul 21 07:05:54 PM PDT 24 Jul 21 07:05:56 PM PDT 24 1420554739 ps
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T235 /workspace/coverage/default/1.rv_dm_smoke.1420410115 Jul 21 07:05:38 PM PDT 24 Jul 21 07:05:46 PM PDT 24 2149428504 ps
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T224 /workspace/coverage/default/38.rv_dm_alert_test.1212129522 Jul 21 07:06:14 PM PDT 24 Jul 21 07:06:16 PM PDT 24 87299027 ps
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T288 /workspace/coverage/default/9.rv_dm_sba_tl_access.2714739573 Jul 21 07:06:05 PM PDT 24 Jul 21 07:06:11 PM PDT 24 3935266515 ps
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T63 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3497962306 Jul 21 05:49:19 PM PDT 24 Jul 21 05:49:22 PM PDT 24 176679516 ps
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T82 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.978652384 Jul 21 05:49:37 PM PDT 24 Jul 21 05:49:43 PM PDT 24 648010824 ps
T85 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3677212783 Jul 21 05:49:47 PM PDT 24 Jul 21 05:49:50 PM PDT 24 121317145 ps
T88 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1874358063 Jul 21 05:49:30 PM PDT 24 Jul 21 05:49:33 PM PDT 24 142682001 ps
T89 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4213854309 Jul 21 05:49:31 PM PDT 24 Jul 21 05:49:33 PM PDT 24 140927131 ps
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T293 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.763616679 Jul 21 05:49:06 PM PDT 24 Jul 21 05:49:08 PM PDT 24 1184360654 ps
T86 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3794779467 Jul 21 05:49:16 PM PDT 24 Jul 21 05:49:22 PM PDT 24 1667303703 ps
T83 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4028022703 Jul 21 05:49:33 PM PDT 24 Jul 21 05:49:35 PM PDT 24 366143263 ps
T294 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1610890876 Jul 21 05:49:06 PM PDT 24 Jul 21 05:50:09 PM PDT 24 85140572014 ps
T79 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1746976355 Jul 21 05:49:12 PM PDT 24 Jul 21 05:49:13 PM PDT 24 130528130 ps
T295 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.207489564 Jul 21 05:49:32 PM PDT 24 Jul 21 05:49:41 PM PDT 24 5764581239 ps
T80 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1548836793 Jul 21 05:48:59 PM PDT 24 Jul 21 05:49:08 PM PDT 24 9742895863 ps
T87 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.793509571 Jul 21 05:49:23 PM PDT 24 Jul 21 05:49:41 PM PDT 24 3319221228 ps
T296 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1564677367 Jul 21 05:49:28 PM PDT 24 Jul 21 05:49:29 PM PDT 24 59310528 ps
T95 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1268346108 Jul 21 05:49:29 PM PDT 24 Jul 21 05:49:33 PM PDT 24 818099819 ps
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