Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254107	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	600739	1		T35	80		T4	6		T7	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	500719	1		T35	80		T4	8		T36	80
values[0x0]	156664	1		T7	14		T5	6		T6	7
values[0x1]	197463	1		T4	1		T7	4		T5	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175389	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	679457	1		T35	80		T4	6		T7	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3172	1		T34	1		T139	1		T56	16
valid_sources[0x01]	3049	1		T57	49		T58	150		T80	6
valid_sources[0x02]	3472	1		T36	1		T56	24		T57	54
valid_sources[0x03]	3596	1		T56	40		T57	42		T58	128
valid_sources[0x04]	3653	1		T37	1		T131	1		T56	5
valid_sources[0x05]	3186	1		T36	1		T6	1		T15	1
valid_sources[0x06]	3569	1		T138	1		T56	23		T57	44
valid_sources[0x07]	3090	1		T36	1		T38	1		T154	1
valid_sources[0x08]	2942	1		T36	1		T12	1		T129	1
valid_sources[0x09]	4574	1		T37	1		T138	3		T56	5
valid_sources[0x0a]	3093	1		T6	3		T37	1		T57	50
valid_sources[0x0b]	4022	1		T34	1		T56	60		T57	37
valid_sources[0x0c]	3774	1		T6	2		T139	1		T138	2
valid_sources[0x0d]	3149	1		T57	38		T58	156		T74	28
valid_sources[0x0e]	2881	1		T21	1		T56	1		T57	42
valid_sources[0x0f]	3316	1		T139	1		T56	37		T57	53
valid_sources[0x10]	3057	1		T36	1		T29	1		T15	3
valid_sources[0x11]	3779	1		T36	2		T37	1		T56	4
valid_sources[0x12]	3618	1		T36	2		T139	2		T56	19
valid_sources[0x13]	3652	1		T19	2		T155	2		T25	1
valid_sources[0x14]	4079	1		T22	1		T131	1		T155	1
valid_sources[0x15]	3627	1		T131	1		T56	32		T57	42
valid_sources[0x16]	3331	1		T7	9		T21	1		T19	1
valid_sources[0x17]	3305	1		T29	1		T139	1		T56	3
valid_sources[0x18]	3391	1		T56	2		T57	37		T58	150
valid_sources[0x19]	3856	1		T56	15		T57	43		T58	119
valid_sources[0x1a]	3104	1		T139	1		T56	10		T57	46
valid_sources[0x1b]	2861	1		T139	1		T154	1		T56	7
valid_sources[0x1c]	3547	1		T56	22		T57	42		T58	82
valid_sources[0x1d]	3206	1		T36	1		T56	1		T57	43
valid_sources[0x1e]	3355	1		T36	1		T131	1		T57	34
valid_sources[0x1f]	3361	1		T22	1		T38	1		T56	46
valid_sources[0x20]	3036	1		T155	1		T56	52		T57	27
valid_sources[0x21]	3874	1		T6	1		T19	5		T56	21
valid_sources[0x22]	3347	1		T36	2		T22	1		T131	1
valid_sources[0x23]	3259	1		T36	2		T6	1		T138	1
valid_sources[0x24]	2793	1		T14	1		T17	40		T56	14
valid_sources[0x25]	3310	1		T56	36		T57	33		T58	119
valid_sources[0x26]	3266	1		T29	1		T156	1		T56	34
valid_sources[0x27]	3501	1		T6	1		T157	5		T56	8
valid_sources[0x28]	3520	1		T56	6		T57	36		T58	164
valid_sources[0x29]	3178	1		T56	71		T57	43		T58	212
valid_sources[0x2a]	3023	1		T34	1		T124	2		T56	35
valid_sources[0x2b]	2964	1		T37	1		T56	28		T57	49
valid_sources[0x2c]	3584	1		T139	1		T129	1		T56	21
valid_sources[0x2d]	2954	1		T36	1		T131	1		T155	2
valid_sources[0x2e]	3021	1		T37	1		T56	23		T57	37
valid_sources[0x2f]	2780	1		T14	1		T57	48		T58	176
valid_sources[0x30]	3891	1		T36	1		T56	3		T57	48
valid_sources[0x31]	4179	1		T36	3		T22	1		T56	43
valid_sources[0x32]	3130	1		T129	1		T56	9		T57	50
valid_sources[0x33]	2869	1		T36	1		T14	1		T56	6
valid_sources[0x34]	3275	1		T37	1		T56	20		T57	48
valid_sources[0x35]	3436	1		T23	1		T139	2		T158	7
valid_sources[0x36]	3279	1		T36	1		T29	1		T131	1
valid_sources[0x37]	4067	1		T29	1		T37	1		T19	2
valid_sources[0x38]	3011	1		T7	1		T38	2		T56	17
valid_sources[0x39]	3750	1		T154	1		T56	21		T57	33
valid_sources[0x3a]	2833	1		T154	2		T56	3		T57	44
valid_sources[0x3b]	3485	1		T34	1		T131	1		T140	1
valid_sources[0x3c]	3075	1		T19	3		T139	1		T56	40
valid_sources[0x3d]	3526	1		T37	2		T56	3		T57	37
valid_sources[0x3e]	3261	1		T154	1		T56	9		T57	49
valid_sources[0x3f]	3114	1		T159	2		T154	1		T56	23
valid_sources[0x40]	3362	1		T7	2		T36	3		T19	1
valid_sources[0x41]	3438	1		T4	2		T139	2		T56	4
valid_sources[0x42]	3064	1		T125	1		T56	17		T57	34
valid_sources[0x43]	3281	1		T36	1		T29	1		T139	1
valid_sources[0x44]	3302	1		T36	1		T131	1		T56	45
valid_sources[0x45]	3026	1		T13	8		T56	10		T57	52
valid_sources[0x46]	3107	1		T37	1		T19	1		T56	22
valid_sources[0x47]	3401	1		T79	1		T139	1		T56	35
valid_sources[0x48]	3653	1		T36	1		T139	2		T14	1
valid_sources[0x49]	3327	1		T56	9		T57	30		T58	162
valid_sources[0x4a]	2959	1		T160	1		T139	2		T56	3
valid_sources[0x4b]	3162	1		T34	1		T37	3		T56	2
valid_sources[0x4c]	3010	1		T34	1		T139	1		T56	16
valid_sources[0x4d]	3026	1		T129	1		T57	49		T58	113
valid_sources[0x4e]	3296	1		T15	20		T139	1		T56	9
valid_sources[0x4f]	3339	1		T36	1		T139	1		T155	2
valid_sources[0x50]	3836	1		T21	1		T131	1		T139	1
valid_sources[0x51]	3292	1		T4	1		T56	37		T57	37
valid_sources[0x52]	3316	1		T125	1		T161	2		T57	50
valid_sources[0x53]	3539	1		T6	1		T31	13		T56	23
valid_sources[0x54]	3492	1		T138	2		T56	21		T57	54
valid_sources[0x55]	3392	1		T6	1		T34	1		T56	13
valid_sources[0x56]	3264	1		T36	1		T22	1		T56	10
valid_sources[0x57]	2974	1		T36	1		T56	12		T57	44
valid_sources[0x58]	4116	1		T36	1		T56	89		T57	28
valid_sources[0x59]	3454	1		T36	1		T56	37		T57	43
valid_sources[0x5a]	3551	1		T12	1		T37	2		T129	1
valid_sources[0x5b]	3354	1		T19	2		T131	1		T56	13
valid_sources[0x5c]	3495	1		T36	1		T21	1		T56	10
valid_sources[0x5d]	3458	1		T157	1		T139	1		T57	40
valid_sources[0x5e]	3115	1		T154	1		T56	40		T57	34
valid_sources[0x5f]	3699	1		T154	1		T56	28		T57	34
valid_sources[0x60]	3219	1		T53	1		T139	1		T136	1
valid_sources[0x61]	3748	1		T38	1		T56	43		T57	67
valid_sources[0x62]	3473	1		T36	1		T6	1		T56	34
valid_sources[0x63]	3405	1		T34	1		T56	40		T57	48
valid_sources[0x64]	3142	1		T15	1		T57	38		T58	104
valid_sources[0x65]	2702	1		T125	1		T129	1		T56	6
valid_sources[0x66]	3656	1		T21	1		T19	4		T125	1
valid_sources[0x67]	3250	1		T36	1		T56	33		T57	34
valid_sources[0x68]	3017	1		T37	1		T139	1		T125	1
valid_sources[0x69]	2988	1		T125	1		T154	1		T56	11
valid_sources[0x6a]	3113	1		T14	1		T56	36		T57	40
valid_sources[0x6b]	3347	1		T36	1		T6	1		T37	1
valid_sources[0x6c]	3522	1		T54	3		T19	1		T138	1
valid_sources[0x6d]	3422	1		T139	2		T138	1		T162	13
valid_sources[0x6e]	2929	1		T36	2		T56	19		T57	45
valid_sources[0x6f]	3533	1		T37	1		T56	37		T57	35
valid_sources[0x70]	2963	1		T79	1		T154	1		T57	39
valid_sources[0x71]	3268	1		T24	41		T56	15		T57	47
valid_sources[0x72]	3366	1		T37	1		T56	9		T57	55
valid_sources[0x73]	3156	1		T56	17		T57	59		T58	152
valid_sources[0x74]	3221	1		T36	1		T37	1		T131	2
valid_sources[0x75]	3358	1		T36	1		T56	29		T57	49
valid_sources[0x76]	3276	1		T22	1		T39	4		T56	31
valid_sources[0x77]	3371	1		T34	1		T57	39		T58	182
valid_sources[0x78]	4323	1		T15	8		T37	1		T139	1
valid_sources[0x79]	3584	1		T123	36		T139	2		T124	5
valid_sources[0x7a]	2745	1		T36	1		T29	1		T56	21
valid_sources[0x7b]	2807	1		T139	1		T56	3		T57	43
valid_sources[0x7c]	3520	1		T6	1		T56	1		T57	31
valid_sources[0x7d]	3484	1		T131	1		T57	41		T58	153
valid_sources[0x7e]	3180	1		T138	1		T40	9		T56	12
valid_sources[0x7f]	2927	1		T125	1		T56	12		T57	47
valid_sources[0x80]	3901	1		T19	2		T56	9		T57	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

299631

1

T35

80

T4

6

T36

80

values[0x0]

all_enables

biggest_size

150819

1

T7

5

T5

2

T6

4

values[0x1]

all_enables

biggest_size

150289

1

T5

1

T6

4

T31

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7074	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	80822	1		T2	1		T3	5		T10	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24953	1		T56	32		T57	65		T58	5867
values[0x0]	30666	1		T1	2		T3	13		T10	3
values[0x1]	32277	1		T2	1		T3	7		T10	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4784	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	83112	1		T2	1		T3	6		T10	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	401	1		T30	1		T140	1		T163	1
valid_sources[0x01]	550	1		T127	1		T58	94		T74	1
valid_sources[0x02]	294	1		T164	1		T125	8		T165	1
valid_sources[0x03]	348	1		T166	1		T167	2		T164	1
valid_sources[0x04]	315	1		T58	80		T74	1		T75	1
valid_sources[0x05]	378	1		T61	1		T168	4		T169	1
valid_sources[0x06]	348	1		T170	1		T57	1		T58	100
valid_sources[0x07]	328	1		T171	1		T58	106		T74	1
valid_sources[0x08]	363	1		T3	5		T30	1		T166	3
valid_sources[0x09]	314	1		T30	1		T172	1		T58	90
valid_sources[0x0a]	271	1		T173	1		T57	1		T58	76
valid_sources[0x0b]	307	1		T61	1		T174	1		T56	1
valid_sources[0x0c]	379	1		T163	1		T175	1		T56	1
valid_sources[0x0d]	300	1		T58	95		T74	1		T75	2
valid_sources[0x0e]	323	1		T176	2		T177	1		T174	2
valid_sources[0x0f]	264	1		T57	2		T58	82		T75	2
valid_sources[0x10]	404	1		T42	5		T178	1		T38	1
valid_sources[0x11]	314	1		T168	1		T179	1		T56	2
valid_sources[0x12]	321	1		T180	1		T169	1		T58	81
valid_sources[0x13]	313	1		T5	3		T131	6		T181	1
valid_sources[0x14]	371	1		T182	1		T163	1		T183	1
valid_sources[0x15]	319	1		T155	1		T184	1		T58	70
valid_sources[0x16]	465	1		T34	1		T185	1		T58	114
valid_sources[0x17]	336	1		T19	1		T186	4		T58	100
valid_sources[0x18]	352	1		T187	7		T169	1		T33	1
valid_sources[0x19]	500	1		T177	2		T58	90		T74	1
valid_sources[0x1a]	355	1		T188	1		T56	1		T58	104
valid_sources[0x1b]	256	1		T189	1		T37	3		T25	1
valid_sources[0x1c]	295	1		T190	1		T179	1		T191	1
valid_sources[0x1d]	319	1		T192	1		T123	2		T58	80
valid_sources[0x1e]	339	1		T193	1		T34	1		T58	95
valid_sources[0x1f]	358	1		T3	1		T34	1		T179	1
valid_sources[0x20]	258	1		T193	1		T57	1		T58	82
valid_sources[0x21]	300	1		T194	1		T190	1		T54	2
valid_sources[0x22]	349	1		T56	1		T58	74		T75	1
valid_sources[0x23]	372	1		T50	1		T195	1		T58	86
valid_sources[0x24]	297	1		T196	1		T58	90		T74	1
valid_sources[0x25]	340	1		T34	1		T127	1		T140	1
valid_sources[0x26]	363	1		T34	1		T197	1		T183	1
valid_sources[0x27]	339	1		T57	1		T58	98		T85	1
valid_sources[0x28]	372	1		T50	1		T179	1		T175	1
valid_sources[0x29]	338	1		T193	1		T198	1		T57	1
valid_sources[0x2a]	296	1		T181	1		T57	1		T58	83
valid_sources[0x2b]	379	1		T58	81		T75	1		T65	30
valid_sources[0x2c]	417	1		T15	1		T56	1		T58	121
valid_sources[0x2d]	301	1		T57	1		T58	85		T121	2
valid_sources[0x2e]	263	1		T199	2		T57	2		T58	87
valid_sources[0x2f]	330	1		T200	1		T201	1		T58	82
valid_sources[0x30]	328	1		T18	1		T182	1		T202	1
valid_sources[0x31]	342	1		T167	3		T198	1		T58	90
valid_sources[0x32]	284	1		T50	2		T176	1		T169	1
valid_sources[0x33]	339	1		T19	1		T23	1		T58	86
valid_sources[0x34]	329	1		T58	88		T72	28		T74	1
valid_sources[0x35]	369	1		T41	1		T203	2		T56	1
valid_sources[0x36]	305	1		T127	1		T136	2		T57	1
valid_sources[0x37]	378	1		T27	1		T204	1		T124	1
valid_sources[0x38]	271	1		T62	1		T193	1		T205	1
valid_sources[0x39]	358	1		T50	1		T22	1		T32	1
valid_sources[0x3a]	317	1		T168	3		T165	1		T57	1
valid_sources[0x3b]	345	1		T174	1		T163	1		T58	88
valid_sources[0x3c]	291	1		T172	1		T191	1		T58	74
valid_sources[0x3d]	328	1		T3	2		T170	1		T16	7
valid_sources[0x3e]	462	1		T57	1		T58	79		T75	1
valid_sources[0x3f]	289	1		T34	1		T206	1		T57	1
valid_sources[0x40]	346	1		T57	1		T58	85		T77	14
valid_sources[0x41]	300	1		T50	1		T58	84		T65	1
valid_sources[0x42]	242	1		T168	1		T57	1		T58	89
valid_sources[0x43]	342	1		T9	1		T174	1		T57	1
valid_sources[0x44]	290	1		T167	1		T56	2		T58	80
valid_sources[0x45]	263	1		T207	1		T171	1		T132	1
valid_sources[0x46]	304	1		T136	1		T58	93		T75	2
valid_sources[0x47]	419	1		T3	1		T167	1		T176	1
valid_sources[0x48]	377	1		T30	1		T208	14		T164	1
valid_sources[0x49]	332	1		T192	2		T57	1		T58	98
valid_sources[0x4a]	445	1		T57	1		T58	87		T86	6
valid_sources[0x4b]	447	1		T167	1		T190	2		T57	2
valid_sources[0x4c]	276	1		T193	1		T37	1		T209	1
valid_sources[0x4d]	404	1		T10	7		T210	7		T54	3
valid_sources[0x4e]	241	1		T18	1		T61	1		T56	1
valid_sources[0x4f]	332	1		T174	1		T56	1		T58	88
valid_sources[0x50]	324	1		T50	1		T34	1		T179	1
valid_sources[0x51]	324	1		T170	2		T58	76		T72	41
valid_sources[0x52]	369	1		T30	1		T174	1		T58	102
valid_sources[0x53]	301	1		T177	1		T58	80		T74	2
valid_sources[0x54]	341	1		T211	1		T17	1		T58	101
valid_sources[0x55]	469	1		T42	2		T188	1		T212	1
valid_sources[0x56]	348	1		T213	1		T173	1		T58	92
valid_sources[0x57]	393	1		T214	12		T58	80		T75	2
valid_sources[0x58]	406	1		T15	1		T174	1		T58	93
valid_sources[0x59]	301	1		T4	1		T215	4		T126	1
valid_sources[0x5a]	311	1		T216	1		T58	86		T121	2
valid_sources[0x5b]	316	1		T169	1		T171	1		T217	1
valid_sources[0x5c]	321	1		T123	1		T56	2		T58	92
valid_sources[0x5d]	314	1		T218	2		T219	1		T58	108
valid_sources[0x5e]	392	1		T181	1		T56	1		T57	1
valid_sources[0x5f]	297	1		T53	1		T138	1		T58	86
valid_sources[0x60]	318	1		T58	93		T74	1		T96	4
valid_sources[0x61]	438	1		T136	1		T58	96		T86	9
valid_sources[0x62]	422	1		T193	1		T167	2		T179	1
valid_sources[0x63]	342	1		T168	1		T220	1		T58	100
valid_sources[0x64]	353	1		T17	1		T156	1		T57	1
valid_sources[0x65]	400	1		T221	5		T216	1		T57	1
valid_sources[0x66]	263	1		T61	1		T222	1		T58	88
valid_sources[0x67]	303	1		T79	1		T135	1		T223	1
valid_sources[0x68]	279	1		T12	9		T179	1		T224	1
valid_sources[0x69]	346	1		T3	2		T57	1		T58	98
valid_sources[0x6a]	344	1		T167	2		T134	5		T225	1
valid_sources[0x6b]	388	1		T211	1		T13	1		T56	1
valid_sources[0x6c]	320	1		T15	1		T69	1		T58	86
valid_sources[0x6d]	396	1		T187	1		T216	2		T56	1
valid_sources[0x6e]	322	1		T56	1		T58	91		T74	1
valid_sources[0x6f]	333	1		T13	4		T226	1		T219	1
valid_sources[0x70]	344	1		T188	1		T168	1		T171	1
valid_sources[0x71]	315	1		T227	1		T58	92		T72	26
valid_sources[0x72]	336	1		T193	1		T57	1		T58	89
valid_sources[0x73]	377	1		T37	2		T58	84		T80	4
valid_sources[0x74]	313	1		T136	1		T57	2		T58	89
valid_sources[0x75]	316	1		T169	1		T57	2		T58	98
valid_sources[0x76]	433	1		T228	8		T56	1		T58	90
valid_sources[0x77]	296	1		T63	1		T54	1		T123	1
valid_sources[0x78]	455	1		T19	1		T175	2		T58	88
valid_sources[0x79]	356	1		T175	1		T216	3		T57	1
valid_sources[0x7a]	332	1		T229	1		T57	1		T58	88
valid_sources[0x7b]	327	1		T18	1		T140	1		T57	1
valid_sources[0x7c]	314	1		T61	1		T180	1		T188	1
valid_sources[0x7d]	357	1		T56	1		T57	1		T58	84
valid_sources[0x7e]	352	1		T120	1		T167	1		T179	1
valid_sources[0x7f]	375	1		T230	8		T171	1		T58	104
valid_sources[0x80]	464	1		T3	1		T34	1		T231	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21436

1

T56

13

T57

21

T58

5509

values[0x0]

all_enables

biggest_size

29712

1

T3

2

T10

3

T35

1

values[0x1]

all_enables

biggest_size

29674

1

T2

1

T3

3

T10

4