SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1054991 | 1 | T4 | 9 | T7 | 18 | T5 | 9 | |||
auto[1] | 135908 | 1 | T35 | 80 | T36 | 80 | T56 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1190690 | 1 | T35 | 80 | T4 | 9 | T7 | 18 | |||
values[1] | 18 | 1 | T74 | 4 | T76 | 1 | T142 | 1 | |||
values[2] | 4 | 1 | T143 | 1 | T144 | 1 | T145 | 1 | |||
values[3] | 120 | 1 | T56 | 4 | T57 | 9 | T74 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1190689 | 1 | T35 | 80 | T4 | 9 | T7 | 18 | |||
values[1] | 17 | 1 | T56 | 2 | T57 | 1 | T146 | 2 | |||
values[2] | 4 | 1 | T56 | 1 | T146 | 1 | T147 | 1 | |||
values[3] | 109 | 1 | T56 | 3 | T57 | 5 | T74 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1190589 | 1 | T35 | 80 | T4 | 9 | T7 | 18 | |||
auto[TlIntgErrCmd] | 100 | 1 | T56 | 3 | T57 | 7 | T74 | 7 | |||
auto[TlIntgErrData] | 101 | 1 | T56 | 3 | T57 | 10 | T74 | 5 | |||
auto[TlIntgErrBoth] | 109 | 1 | T56 | 4 | T57 | 3 | T74 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 221379 | 0 | T1 | 2 | T2 | 1 | T3 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 221161 | 1 | T1 | 2 | T2 | 1 | T3 | 20 | |||
values[1] | 19 | 1 | T56 | 1 | T57 | 2 | T74 | 3 | |||
values[2] | 4 | 1 | T74 | 1 | T144 | 1 | T148 | 1 | |||
values[3] | 106 | 1 | T56 | 6 | T57 | 4 | T74 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 221183 | 1 | T1 | 2 | T2 | 1 | T3 | 20 | |||
values[1] | 17 | 1 | T56 | 1 | T57 | 1 | T74 | 1 | |||
values[2] | 7 | 1 | T57 | 2 | T146 | 2 | T144 | 1 | |||
values[3] | 96 | 1 | T56 | 3 | T57 | 6 | T74 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 221069 | 1 | T1 | 2 | T2 | 1 | T3 | 20 | |||
auto[TlIntgErrCmd] | 114 | 1 | T56 | 4 | T57 | 7 | T74 | 11 | |||
auto[TlIntgErrData] | 92 | 1 | T56 | 2 | T57 | 9 | T74 | 4 | |||
auto[TlIntgErrBoth] | 104 | 1 | T56 | 4 | T57 | 4 | T74 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |