Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 578484 1 T4 3 T7 13 T5 5
full_word 612415 1 T35 80 T4 6 T7 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 1190589 1 T35 80 T4 9 T7 18
auto[TlIntgErrCmd] 100 1 T56 3 T57 7 T74 7
auto[TlIntgErrData] 101 1 T56 3 T57 10 T74 5
auto[TlIntgErrBoth] 109 1 T56 4 T57 3 T74 8



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 514645 1 T35 80 T4 8 T36 80
auto[1] 676254 1 T4 1 T7 18 T5 8



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 213403 1 T4 2 T6 3 T29 5
auto[TlIntgErrNone] partial auto[1] 364793 1 T4 1 T7 13 T5 5
auto[TlIntgErrNone] full_word auto[0] 301087 1 T35 80 T4 6 T36 80
auto[TlIntgErrNone] full_word auto[1] 311306 1 T7 5 T5 3 T6 8
auto[TlIntgErrCmd] partial auto[0] 47 1 T56 2 T57 2 T74 3
auto[TlIntgErrCmd] partial auto[1] 49 1 T56 1 T57 5 T74 4
auto[TlIntgErrCmd] full_word auto[0] 2 1 T144 1 T149 1 - -
auto[TlIntgErrCmd] full_word auto[1] 2 1 T76 1 T150 1 - -
auto[TlIntgErrData] partial auto[0] 54 1 T56 1 T57 3 T74 4
auto[TlIntgErrData] partial auto[1] 41 1 T56 2 T57 5 T74 1
auto[TlIntgErrData] full_word auto[0] 3 1 T57 1 T76 1 T144 1
auto[TlIntgErrData] full_word auto[1] 3 1 T57 1 T76 1 T147 1
auto[TlIntgErrBoth] partial auto[0] 43 1 T56 2 T57 2 T74 4
auto[TlIntgErrBoth] partial auto[1] 54 1 T56 2 T57 1 T74 3
auto[TlIntgErrBoth] full_word auto[0] 6 1 T74 1 T146 1 T143 1
auto[TlIntgErrBoth] full_word auto[1] 6 1 T76 1 T146 1 T151 1

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